List of Figures

1. Graphical representation of binary and multiple-valued logic levels.
2. The binary inverter is utilized to handle multiple input-signals, by capacitively connecting the inputs to the gate. In (a) the schematic is shown, and in (b) the symbol.
3. A capacitive equivalent circuit for an nMOS-transistor, which includes most of the paracitic capacitances seen from the floating-gate.
4. The floating-gate binary is modified to become a multiple-valued floating-gate inverter by adding a capacitor, $C_{\textnormal{\tiny{f}}}$, between the output and the floating-gate.
5. A simplified multiple-valued inverter design. The floating-gate is affected by voltage changes at both the input and the output.
6. A parametric simulation which demonstrates how $C_{\textnormal{\tiny{f}}}$ changes the gain of the multiple-valued inverter. The $C_{\textnormal{\tiny{i}}}$ is held constant (10 fF) while $C_{\textnormal{\tiny{f}}}$ is linearly stepped from 5 fF to 20 fF. As the simulation demonstrates, increased $C_{\textnormal{\tiny{f}}}$ decreases the gain and vice versa.
7. Simulation results of a single-input multiple-valued inverter using the parasitic capacitance, $C_{\textnormal{\tiny{gd}}}$, as the replacement for the $C_{\textnormal{\tiny{f}}}$. The input capacitance, $C_{\textnormal{\tiny{i}}}$, equals 13 fF while the transistor sizes are 10/1.2 $\mu m$ and 25/1.2 $\mu m$ for nMOS and pMOS, respectively.
8. Measurement of a single-input multiple-valued inverter. The capacitor values are $C_{\textnormal{\tiny{i}}}$ = 10 fF and $C_{\textnormal{\tiny{f}}}$ $\approx$ 9 fF, while the transistor sizes are 1.0/1.2 $\mu$ for nMOS and 2.5/1.2 for pMOS. Further measurements with different supply voltages are shown in Appendix F.
9. The gain of a single-input multiple-valued inverter. The supply voltage is 2.0V. The plot clearly shows the non-linear characterization near the rails. The gain plot of other supply voltages is shown in Appendix F.
10. A initializing scheme with a bias ( $V_{\textnormal{\tiny{bias}}}$) for the floating-gates, where $\phi_{\textnormal{\tiny{p}}}$ indicates the initializing time.
11. A initializing scheme for the floating-gate of the multiple-valued inverter. The initializing scheme is carried out by adding a switch between the output and the floating-gate. In (a) the schematic is shown and in (b) the symbol.
12. The multiple-valued recharge inverter is measured with a radix-8 input-signal and a 2.0V supply voltage. In the lowest plot the output is inverted and plotted with the input. The capacitance values are $C_{\textnormal{\tiny{i}}}$ = 10 fF and $C_{\textnormal{\tiny{f}}}$ $\approx$ 9 fF, while the recharge transistor sizes are 0.8/0.6 $\mu$ for nMOS and 0.8/0.6 for pMOS.
13. The voltage division of a step between two random logical levels, e.g. n and n+1. $V_{\textnormal{\tiny{trig}}}$ is the voltage needed for a binary inverter to switch.
14. The 3D-plot shows the gain of different output signals as a function of the supply voltage ( $V_{\textnormal{\tiny{dd}}}$). It can furthermore be directly translated to demonstrate the linear voltage range.
15. A Binary-to-Multiple-Valued Converter. The circuit converts three recharge binary signals to one radix-8 signal. The capacitance values are $C_{1}$ = C, $C_{2} = 2C$, $C_{3}$ = 4C and $C_{\textnormal{\tiny{f}}}$ $\approx$ 7C, where C is the unit capacitance value.
16. Truth table for a 3-bit BMVC.
17. Measurements of a 3-bit (radix-8) Binary-to-Multiple-Valued Converter. The transistor sizes are the same as in previous chapter, while the unit capacitor (C) is 10.13 fF.
18. Auto-zeroing circuit used to convert binary signal to include a recharge period. Measurements of this design are presented in Appendix F.
19. The (radix-8) Multiple-valued-to-Binary converter. The capacitances values are $C_{0}$ = $C_{1}$ = $C_{5}$ = $C_{5}$ = $C_{6}$ = C, $C_{2}$ = 3/4 fF, $C_{3}$ = 7/3 fF, $C_{7}$ = 3/2 fF.
20. Measurements of the MVBC. We believe the shifted recharge level and the poor pull-down is due to the characterization of the buffer element used at the outputs. The capacitances values are $C_{0}$ = $C_{1}$ = $C_{5}$ = $C_{5}$ = $C_{6}$ = 10 fF, $C_{2}$ = 13.3 fF, $C_{3}$ = 23.3 fF, $C_{7}$ = 15 fF and the transistor dimentions are kept the same as for previous examples.
21. The truth table for a radix-8 MVBC.
22. A multiple-valued recharge adder. The adder is completely based on the circuits presented in Chapter 2, only the number of capacitances and their values are changed. The capacitance values are for a radix-R design is $C_{1}$ = $C_{2}$ = (R-1)C, $C_{3}$ = $C_{8}$ = C, $C_{4}$ = (2R-1)C, $C_{5}$ = 5C, $C_{6}$ = [R/(R-1)]C and $C_{7}$ = [(2R-1)/(R-1)]C, where C represents the unit capacitor.
23. Simulation for a radix-8 adder. The input B is at all times equal to ``0'', and the capacitance values are computed based on the equations given in the caption of Figure 3.8.
24. The design shows a buffer implementation, intended as an illustration for the latch description provided in the text.
25. A graphical description of the signal propagation through the design in Figure 4.1.
26. A proposed use of the recharge signal to construct a binary latch with only two binary recharge inverters.
27. Signal propagation through the latch design in Figure 4.3.
28. The multiple-valued latch constructed in the same manner as in Figure 4.3, but only with multiple-valued inverters instead of binary inverters.
29. Measurements of the circuit in Figure 4.5. In the lowest plot the output is manipulated, thus phase-shifted and inverted, so that it is easier to see the latched signal in relation to the input.
30. Another variation of the latch implementation. This design strategy makes it easier to separate the latches from the others, and furthermore the circuits are operating on the same recharge signal.
31. Two possible clock skew situations. In (a) the clock signal $\overline {\phi }$ arrives $\Delta t$ later than expected, we therefore denote that time as +$\Delta t$, while in (b) the clock signal $\overline {\phi }$ arrives $\Delta t$ earlier than expected, hence -$\Delta t$ .
32. Measurement of the first clock skew. As indicated the design would for periods of time act as a buffer. Since neither of the clock signals alone can be used to determine the valid period of the buffer, this phenomenon may be considered to be a malfunction.
33. Measurement of the second clock skew. As it indicates, the design would for periods of time be latching the input-signal. Since neither of the clock signals alone can be used to determine the valid period of the latch, this phenomenon may be considered to be a malfuntion.
34. Measurements of a single-phase clocking scheme used in the design in Figure 4.7. The output indicates a small attenuation of the input-voltage change.
35. The ternary clocking scheme (in the bottom of the figure) is constructed based upon the two non-overlapping clocking schemes.
36. A proposal for a multiple-valued clock generator. The signals are as follows; A = $\phi _{1}\cdot \overline {\phi _{2}}$ and B = $\overline {\phi _{1}}\cdot \phi _{2}$ and recharge = $\overline {\phi _{1}}\cdot \overline {\phi _{2}}$.
37. Simulation result of the circuit in Figure 4.7 with the ternary clock signal.
38. The multiple-input multiple-valued recharge latch. By using the capacitively coupled input feature we can mix input-signals (in the same manner as in Chapter 3) to create multiple-valued adders and converters that incorporate latches without any additional elements or circuits.
39. A cascaded multiple-valued inverter chain.
40. Simulation results of 14 cascaded single-input multiple-valued inverters. Here the simulation clearly unveils the domino effect of the design.
41. A straight-forward design of a multiple-valued D-latch.
42. A multiple-valued D-latch constructed by using two multiple-valued latches. In this design one can extract outputs which follows a $\phi$ and a $\overline {\phi }$ recharge period.
43. This D-latch is a simplified version of the circuit shown in Figure 4.19. Notice that each of the multiple-valued inverters are actually operating on the opposite recharge clock, and hence both are latching each other's output signal.
44. The ideal signal propagation through the D-latch design depicted in Figure 4.20.
45. A proposal for a multiple-valued recharge D-latch, implemented with the BMVC and the MVBC designs.
46. This design avoids the additional multiple-valued inverter at the output of the BMVC in Figure 4.22, by applying the $\overline {\phi }$ recharge signal to the BMVC, and hence latching the signals sent by the MVBC.
47. Measurement of the leakage for a single-input multiple-valued recharge inverter.
48. The maximum frequency for the multiple-valued inverter as a function of $V_{\textnormal{\tiny{dd}}}$.
49. The current for both a binary and a multiple-valued inverter .
50. A single-bit binary full adder.
51. The design illustrates how two input-signals should be weighted with respect to their radices (assuming that they have the same significance).
52. The two input multiple-valued recharge circuit. In (a) the schematic is shown, while in (b) its corresponding truth table.
53. The bounding diagram for the prototype chip. Notice to the connection from pad 51 to the cavity, the connection is used for asserting $V_{\textnormal{\tiny{ss}}}$ at the cavity.
54. Die photography of the prototype chip.
55. The prototype chip was placed on a print board.
56. The first test setup. Primarily used for testing out our ideas with discrete components.
57. Map of the first GPIB network. This configuration was used to take measurements of the discrete components before designing the prototype chip.
58. The second test setup.
59. Map of the second GPIB network. This configuration was used for measurements of the test chip. Agilent 33120As and 33250As were all synchronized.
60. The third test setup.
61. Map of the third and last GPIB network. This configuration is a result of newly purchased instruments, TTi TGA1244, and the removal of the instruments used previously (the Agilent 33120As).
62. A standard layout design proposal for the multiple-valued recharge inverter, with the purpose to test out its adaptability to synthesis.
63. A layout proposal for the multiple-valued recharge inverter, with as few as possible junction contacts at the semi-floating-gate.
64. Another layout proposal for the multiple-valued recharge inverter, with as few as possible junction contacts at the semi-floating-gate. Notice the recharge switch is implemented by a transmission gate.
65. Another layout proposal for the multiple-valued recharge inverter, quite similar to the other two proposals. In this design we have implemented smaller transistor sizes for the inverter.
66. A proposal for the implementation of a MOS-capacitor. The MOS-transistor is used both as the input capacitance $C_{\textnormal{\tiny{i}}}$ and as the feedback $C_{\textnormal{\tiny{f}}}$.
67. A unusual use of the parasitic coupling capacitor. Here we have used it as a replacement for the feedback capacitor, and it yields 2.4 fF with the dimensions 6x3.5 $\mu$m.
68. The discrete components and their setup is shown. These were used for a first order evaluation of some of our ideas. After a satisfying confirmation of the theory the prototype chip where designed and processed.
69. Measurement of a single-input multiple-valued recharge inverter with different supply voltages, thus 1.8V, 2V, 2.5V, 3.0V, 3.5V, 4.0V, 4.5V, 5.0V. The plot clearly demonstrates the linear voltage range and its dependency on the supply voltage. Furthermore, the same data set were used to create the 3D-plot in Figure 2.13.
70. The linear voltage span deduced from the data used in Figure F.1. We have defined that the linear voltage span is where the gain of the circuit is between <-1.1, -0.8>.
71. The relative linear range as a function of the supply voltage.
72. Measurement from the discrete components. The test circuit were a single-input multiple-valued recharge inverter with a supply voltage of 2.0 V. The capacitances were $C_{\textnormal{\tiny{i}}}$ = 2.7 nF and $C_{\textnormal{\tiny{f}}}$ = 2.1 nF.
73. The corresponding gain plot of Figure F.4.
74. Measurement from the discrete components. The test circuit were a three-input Binary-to-Multiple-Valued Converter (BMVC) with a supply voltage of 3.0 V. The capacitances were $C_{\textnormal{\tiny{i}}}$ = [(1)(2)(4)] and $C_{\textnormal{\tiny{f}}}$ = 6.26 nF.
75. The corresponding gain plot of Figure F.6.
76. Measurement from the discrete components. The test circuit were a single-input multiple-valued recharge inverter with a supply voltage of 2.0 V. The capacitances were $C_{\textnormal{\tiny{i}}}$ = 1 nF and $C_{\textnormal{\tiny{f}}}$ = 0.86 nF.
77. The corresponding gain plot of Figure F.8.
78. Measurement of the AutoZero circuit on the prototype chip with a supply voltage of 2.0V.
79. Measurement of the AutoZero circuit on the prototype chip with a supply voltage of 3.0V.
80. Measurement of the AutoZero circuit on the prototype chip with a supply voltage of 4.0V.
81. Measurement of the AutoZero circuit on the prototype chip with a supply voltage of 5.0V.
82. Measurement of a single-input multiple-valued latch with a radix-16 input signal and a supply-voltage of 2.0 V.
83. Measurement of a single-input multiple-valued latch with a radix-32 input signal and a supply-voltage of 2.0 V.
84. Measurement of a single-input multiple-valued latch with a radix-8 input signal and a supply-voltage of 2.0 V.
85. Measurement of a single-input multiple-valued latch with a radix-10 input signal and a supply-voltage of 2.0 V. The output is manipulated, thus inverted and phase-shifted.
86. Measurement of a single-input multiple-valued latch with a radix-16 input signal and a supply-voltage of 2.0 V. The output is manipulated, thus inverted and phase-shifted.
87. Measurement of a single-input multiple-valued latch with a radix-32 input signal and a supply-voltage of 2.0 V. The output is manipulated, thus inverted and phase-shifted.
88. Measurement of a single-input multiple-valued latch with a radix-8 input signal and a supply-voltage of 2.0 V. The output is manipulated, thus inverted and phase-shifted.
89. Measurement of a single-input multiple-valued latch with a radix-11 input signal and a supply-voltage of 2.0 V. The output is manipulated, thus inverted and phase-shifted.
90. The buffer design implemented on the prototype chip were a operational amplifier. Due to a mistake in coupling the input signals the operational amplifier did not work as specified in our original plan.
91. The output of a single-input multiple-valued recharge inverter is sent through the buffer. The output is inverted (in Matlab) and plotted.
92. The different currents for both a binary and a multiple-valued inverter.