diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile --- linux/drivers/net/sk98lin/Makefile 2004-08-14 12:54:46.000000000 +0200 +++ linux-new/drivers/net/sk98lin/Makefile 2004-09-07 13:33:32.091610065 +0200 @@ -1,6 +1,56 @@ +#****************************************************************************** # -# Makefile for the SysKonnect SK-98xx device driver. +# Name: skge.c +# Project: GEnesis, PCI Gigabit Ethernet Adapter +# Version: $Revision: 1.9 $ +# Date: $Date: 2004/07/13 15:54:50 $ +# Purpose: The main driver source module # +#****************************************************************************** + +#****************************************************************************** +# +# (C)Copyright 1998-2002 SysKonnect GmbH. +# (C)Copyright 2002-2004 Marvell. +# +# Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet +# Server Adapter driver. (Kernel 2.6) +# +# Author: Mirko Lindner (mlindner@syskonnect.de) +# Ralph Roesler (rroesler@syskonnect.de) +# +# Address all question to: linux@syskonnect.de +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# The information in this file is provided "AS IS" without warranty. +# +#****************************************************************************** + +#****************************************************************************** +# +# History: +# +# $Log: Makefile2.6,v $ +# Revision 1.9 2004/07/13 15:54:50 rroesler +# Add: file skethtool.c +# Fix: corrected header regarding copyright +# Fix: minor typos corrected +# +# Revision 1.8 2004/06/08 08:39:38 mlindner +# Fix: Add CONFIG_SK98LIN_ZEROCOPY as default +# +# Revision 1.7 2004/06/03 16:06:56 mlindner +# Fix: Added compile flag SK_DIAG_SUPPORT +# +# Revision 1.6 2004/06/02 08:02:59 mlindner +# Add: Changed header information and inserted a GPL statement +# +# +#****************************************************************************** # @@ -13,13 +63,16 @@ obj-$(CONFIG_SK98LIN) += sk98lin.o sk98lin-objs := \ skge.o \ + sky2.o \ + skethtool.o \ + sky2le.o \ skdim.o \ skaddr.o \ skgehwt.o \ skgeinit.o \ skgepnmi.o \ skgesirq.o \ - ski2c.o \ + sktwsi.o \ sklm80.o \ skqueue.o \ skrlmt.o \ @@ -76,13 +129,11 @@ # SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources # SK_DBGCAT_DRV_EVENT 0x08000000 driver events -EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DSK_USE_CSUM -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM) +EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \ + -DGENESIS -DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \ + $(DBGDEF) $(SKPARAM) clean: rm -f core *.o *.a *.s - - - - diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h --- linux/drivers/net/sk98lin/h/lm80.h 2004-08-14 12:56:09.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/lm80.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: lm80.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.6 $ - * Date: $Date: 2003/05/13 17:26:52 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:08 $ * Purpose: Contains all defines for the LM80 Chip * (National Semiconductor). * diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h --- linux/drivers/net/sk98lin/h/skaddr.h 2004-08-14 12:55:33.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skaddr.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skaddr.h * Project: Gigabit Ethernet Adapters, ADDR-Modul - * Version: $Revision: 1.29 $ - * Date: $Date: 2003/05/13 16:57:24 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:07 $ * Purpose: Header file for Address Management (MC, UC, Prom). * ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h --- linux/drivers/net/sk98lin/h/skcsum.h 2004-08-14 12:54:48.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skcsum.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skcsum.h * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx) - * Version: $Revision: 1.10 $ - * Date: $Date: 2003/08/20 13:59:57 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2003/12/29 15:37:26 $ * Purpose: Store/verify Internet checksum in send/receive packets. * ******************************************************************************/ @@ -157,9 +157,7 @@ typedef struct s_Csum { /* Enabled receive SK_PROTO_XXX bit flags. */ unsigned ReceiveFlags[SK_MAX_NETS]; -#ifdef TX_CSUM unsigned TransmitFlags[SK_MAX_NETS]; -#endif /* TX_CSUM */ /* The protocol statistics structure; one per supported protocol. */ SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS]; diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h --- linux/drivers/net/sk98lin/h/skdebug.h 2004-08-14 12:55:32.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skdebug.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skdebug.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.14 $ - * Date: $Date: 2003/05/13 17:26:00 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2004/02/26 16:06:06 $ * Purpose: SK specific DEBUG support * ******************************************************************************/ @@ -58,6 +58,9 @@ #define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */ #define SK_DBGMOD_PECP 0x00000100L /* PECP module */ #define SK_DBGMOD_POWM 0x00000200L /* Power Management module */ +#ifdef SK_ASF +#define SK_DBGMOD_ASF 0x00000400L /* ASF module */ +#endif /* Debug events */ diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h --- linux/drivers/net/sk98lin/h/skdrv1st.h 2004-08-14 12:54:47.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skdrv1st.h 2004-08-26 10:28:00.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skdrv1st.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.4 $ - * Date: $Date: 2003/11/12 14:28:14 $ + * Version: $Revision: 1.5 $ + * Date: $Date: 2004/08/25 13:26:39 $ * Purpose: First header file for driver and all other modules * ******************************************************************************/ @@ -22,20 +22,6 @@ * ******************************************************************************/ -/****************************************************************************** - * - * Description: - * - * This is the first include file of the driver, which includes all - * neccessary system header files and some of the GEnesis header files. - * It also defines some basic items. - * - * Include File Hierarchy: - * - * see skge.c - * - ******************************************************************************/ - #ifndef __INC_SKDRV1ST_H #define __INC_SKDRV1ST_H @@ -58,6 +44,7 @@ #define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6)) + #include #include #include @@ -90,6 +77,10 @@ #include "h/lm80.h" #include "h/xmac_ii.h" +#ifndef SK_BMU_RX_WM_PEX +#define SK_BMU_RX_WM_PEX 0x80 +#endif + #ifdef __LITTLE_ENDIAN #define SK_LITTLE_ENDIAN #else @@ -188,3 +179,8 @@ #endif +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h --- linux/drivers/net/sk98lin/h/skdrv2nd.h 2004-09-07 13:32:31.460547840 +0200 +++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h 2004-08-26 10:28:00.000000000 +0200 @@ -1,17 +1,17 @@ /****************************************************************************** * - * Name: skdrv2nd.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.10 $ - * Date: $Date: 2003/12/11 16:04:45 $ - * Purpose: Second header file for driver and all other modules + * Name: skdrv2nd.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.29 $ + * Date: $Date: 2004/08/25 13:26:05 $ + * Purpose: Second header file for driver and all other modules * ******************************************************************************/ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect GmbH. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -42,10 +42,11 @@ #include "h/skqueue.h" #include "h/skgehwt.h" #include "h/sktimer.h" -#include "h/ski2c.h" +#include "h/sktwsi.h" #include "h/skgepnmi.h" #include "h/skvpd.h" #include "h/skgehw.h" +#include "h/sky2le.h" #include "h/skgeinit.h" #include "h/skaddr.h" #include "h/skgesirq.h" @@ -53,104 +54,121 @@ #include "h/skrlmt.h" #include "h/skgedrv.h" +/****************************************************************************** + * + * Generic ISR defines + * + ******************************************************************************/ -extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); -extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); -extern SK_U64 SkOsGetTime(SK_AC*); -extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); -extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); -extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); -extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); -extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); -extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); -extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); - -#ifdef SK_DIAG_SUPPORT -extern int SkDrvEnterDiagMode(SK_AC *pAc); -extern int SkDrvLeaveDiagMode(SK_AC *pAc); -#endif +#define SkIsrRetVar irqreturn_t +#define SkIsrRetNone IRQ_NONE +#define SkIsrRetHandled IRQ_HANDLED + +#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb) +#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb) +#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb) + +/****************************************************************************** + * + * Global function prototypes + * + ******************************************************************************/ + +extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); +extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); +extern SK_U64 SkOsGetTime(SK_AC*); +extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); +extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); +extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); +extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); +extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); +extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); +extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); +extern int SkDrvEnterDiagMode(SK_AC *pAc); +extern int SkDrvLeaveDiagMode(SK_AC *pAc); + +/****************************************************************************** + * + * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)! + * + ******************************************************************************/ struct s_DrvRlmtMbuf { - SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ - SK_U8 *pData; /* Data buffer (virtually contig.). */ - unsigned Size; /* Data buffer size. */ - unsigned Length; /* Length of packet (<= Size). */ - SK_U32 PortIdx; /* Receiving/transmitting port. */ + SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ + SK_U8 *pData; /* Data buffer (virtually contig.). */ + unsigned Size; /* Data buffer size. */ + unsigned Length; /* Length of packet (<= Size). */ + SK_U32 PortIdx; /* Receiving/transmitting port. */ #ifdef SK_RLMT_MBUF_PRIVATE - SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ -#endif /* SK_RLMT_MBUF_PRIVATE */ - struct sk_buff *pOs; /* Pointer to message block */ + SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ +#endif + struct sk_buff *pOs; /* Pointer to message block */ }; +/****************************************************************************** + * + * Linux specific TIME defines + * + ******************************************************************************/ -/* - * Time macros - */ #if SK_TICKS_PER_SEC == 100 #define SK_PNMI_HUNDREDS_SEC(t) (t) #else -#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \ - (SK_TICKS_PER_SEC)) +#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC)) #endif -/* - * New SkOsGetTime - */ #define SkOsGetTimeCurrent(pAC, pUsec) {\ struct timeval t;\ do_gettimeofday(&t);\ *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\ } +/****************************************************************************** + * + * Linux specific IOCTL defines and typedefs + * + ******************************************************************************/ -/* - * ioctl definitions - */ -#define SK_IOCTL_BASE (SIOCDEVPRIVATE) -#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) -#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) -#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) -#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3) -#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4) - -typedef struct s_IOCTL SK_GE_IOCTL; +#define SK_IOCTL_BASE (SIOCDEVPRIVATE) +#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) +#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) +#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) +#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3) +#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4) +typedef struct s_IOCTL SK_GE_IOCTL; struct s_IOCTL { char __user * pData; unsigned int Len; }; +/****************************************************************************** + * + * Generic sizes and length definitions + * + ******************************************************************************/ + +#define TX_RING_SIZE (24*1024) /* GEnesis/Yukon */ +#define RX_RING_SIZE (24*1024) /* GEnesis/Yukon */ +#define RX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */ +#define TX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */ + +#define ETH_BUF_SIZE 1560 /* multiples of 8 bytes */ +#define ETH_MAX_MTU 1514 +#define ETH_MIN_MTU 60 +#define ETH_MULTICAST_BIT 0x01 +#define SK_JUMBO_MTU 9000 + +#define TX_PRIO_LOW 0 /* asynchronous queue */ +#define TX_PRIO_HIGH 1 /* synchronous queue */ +#define DESCR_ALIGN 64 /* alignment of Rx/Tx descriptors */ + +/****************************************************************************** + * + * PNMI related definitions + * + ******************************************************************************/ -/* - * define sizes of descriptor rings in bytes - */ - -#define TX_RING_SIZE (8*1024) -#define RX_RING_SIZE (24*1024) - -/* - * Buffer size for ethernet packets - */ -#define ETH_BUF_SIZE 1540 -#define ETH_MAX_MTU 1514 -#define ETH_MIN_MTU 60 -#define ETH_MULTICAST_BIT 0x01 -#define SK_JUMBO_MTU 9000 - -/* - * transmit priority selects the queue: LOW=asynchron, HIGH=synchron - */ -#define TX_PRIO_LOW 0 -#define TX_PRIO_HIGH 1 - -/* - * alignment of rx/tx descriptors - */ -#define DESCR_ALIGN 64 - -/* - * definitions for pnmi. TODO - */ #define SK_DRIVER_RESET(pAC, IoC) 0 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0 #define SK_DRIVER_SELFTEST(pAC, IoC) 0 @@ -159,20 +177,16 @@ #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0 -/* -** Interim definition of SK_DRV_TIMER placed in this file until -** common modules have boon finallized -*/ -#define SK_DRV_TIMER 11 -#define SK_DRV_MODERATION_TIMER 1 -#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */ -#define SK_DRV_RX_CLEANUP_TIMER 2 -#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */ - -/* -** Definitions regarding transmitting frames -** any calculating any checksum. -*/ + +/****************************************************************************** + * + * Various offsets and sizes + * + ******************************************************************************/ + +#define SK_DRV_MODERATION_TIMER 1 /* id */ +#define SK_DRV_MODERATION_TIMER_LENGTH 1 /* 1 second */ + #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6 #define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6 #define C_LEN_ETHERMAC_HEADER_LENTYPE 2 @@ -198,114 +212,341 @@ #define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */ #define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */ -/* TX and RX descriptors *****************************************************/ +/****************************************************************************** + * + * Tx and Rx descriptor definitions + * + ******************************************************************************/ typedef struct s_RxD RXD; /* the receive descriptor */ - struct s_RxD { - volatile SK_U32 RBControl; /* Receive Buffer Control */ - SK_U32 VNextRxd; /* Next receive descriptor,low dword */ - SK_U32 VDataLow; /* Receive buffer Addr, low dword */ - SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ - SK_U32 FrameStat; /* Receive Frame Status word */ - SK_U32 TimeStamp; /* Time stamp from XMAC */ - SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ - SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ - RXD *pNextRxd; /* Pointer to next Rxd */ - struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ + volatile SK_U32 RBControl; /* Receive Buffer Control */ + SK_U32 VNextRxd; /* Next receive descriptor,low dword */ + SK_U32 VDataLow; /* Receive buffer Addr, low dword */ + SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ + SK_U32 FrameStat; /* Receive Frame Status word */ + SK_U32 TimeStamp; /* Time stamp from XMAC */ + SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ + SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ + RXD *pNextRxd; /* Pointer to next Rxd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ }; typedef struct s_TxD TXD; /* the transmit descriptor */ - struct s_TxD { - volatile SK_U32 TBControl; /* Transmit Buffer Control */ - SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ - SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ - SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ - SK_U32 FrameStat; /* Transmit Frame Status Word */ - SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ - SK_U16 TcpSumSt; /* TCP Sum Start */ - SK_U16 TcpSumWr; /* TCP Sum Write */ - SK_U32 TcpReserved; /* not used */ - TXD *pNextTxd; /* Pointer to next Txd */ - struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ + volatile SK_U32 TBControl; /* Transmit Buffer Control */ + SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ + SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ + SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ + SK_U32 FrameStat; /* Transmit Frame Status Word */ + SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ + SK_U16 TcpSumSt; /* TCP Sum Start */ + SK_U16 TcpSumWr; /* TCP Sum Write */ + SK_U32 TcpReserved; /* not used */ + TXD *pNextTxd; /* Pointer to next Txd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ }; -/* Used interrupt bits in the interrupts source register *********************/ +/****************************************************************************** + * + * Generic Yukon-II defines + * + ******************************************************************************/ -#define DRIVER_IRQS ((IS_IRQ_SW) | \ - (IS_R1_F) |(IS_R2_F) | \ - (IS_XS1_F) |(IS_XA1_F) | \ - (IS_XS2_F) |(IS_XA2_F)) - -#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \ - (IS_EXT_REG) |(IS_TIMINT) | \ - (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \ - (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \ - (IS_MAC1) |(IS_LNK_SYNC_M1)| \ - (IS_MAC2) |(IS_LNK_SYNC_M2)| \ - (IS_R1_C) |(IS_R2_C) | \ - (IS_XS1_C) |(IS_XA1_C) | \ - (IS_XS2_C) |(IS_XA2_C)) - -#define IRQ_MASK ((IS_IRQ_SW) | \ - (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \ - (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \ - (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \ - (IS_HW_ERR) |(IS_I2C_READY)| \ - (IS_EXT_REG) |(IS_TIMINT) | \ - (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \ - (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \ - (IS_MAC1) |(IS_MAC2) | \ - (IS_R1_C) |(IS_R2_C) | \ - (IS_XS1_C) |(IS_XA1_C) | \ - (IS_XS2_C) |(IS_XA2_C)) +#define LE_SIZE sizeof(SK_HWLE) +#define MAX_NUM_FRAGS (MAX_SKB_FRAGS + 1) +#define MIN_LEN_OF_LE_TAB 128 +#define MAX_LEN_OF_LE_TAB 4096 +#define MAX_UNUSED_RX_LE_WORKING 8 +#ifdef MAX_FRAG_OVERHEAD +#undef MAX_FRAG_OVERHEAD +#define MAX_FRAG_OVERHEAD 4 +#endif +// as we have a maximum of 16 physical fragments, +// maximum 1 ADDR64 per physical fragment +// maximum 4 LEs for VLAN, Csum, LargeSend, Packet +#define MIN_LE_FREE_REQUIRED ((16*2) + 4) +#define IS_GMAC(pAc) (!pAc->GIni.GIGenesis) +#ifdef USE_SYNC_TX_QUEUE +#define TXS_MAX_LE 256 +#else /* !USE_SYNC_TX_QUEUE */ +#define TXS_MAX_LE 0 +#endif -#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */ +#define ETHER_MAC_HDR_LEN (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE +#define IP_HDR_LEN 20 +#define TCP_CSUM_OFFS 0x10 +#define UDP_CSUM_OFFS 0x06 +#define TXA_MAX_LE 256 +#define RX_MAX_LE 256 +#define ST_MAX_LE (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE)) + +/****************************************************************************** + * + * Structures specific for Yukon-II + * + ******************************************************************************/ + +typedef struct s_frag SK_FRAG; +struct s_frag { + SK_FRAG *pNext; + char *pVirt; + SK_U64 pPhys; + unsigned int FragLen; +}; + +typedef struct s_packet SK_PACKET; +struct s_packet { + /* Common infos: */ + SK_PACKET *pNext; /* pointer for packet queues */ + unsigned int PacketLen; /* length of packet */ + unsigned int NumFrags; /* nbr of fragments (for Rx always 1) */ + SK_FRAG *pFrag; /* fragment list */ + SK_FRAG FragArray[MAX_NUM_FRAGS]; /* TX fragment array */ + unsigned int NextLE; /* next LE to use for the next packet */ + + /* Private infos: */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ +}; + +typedef struct s_queue SK_PKT_QUEUE; +struct s_queue { + SK_PACKET *pHead; + SK_PACKET *pTail; + spinlock_t QueueLock; /* serialize packet accesses */ +}; + +/******************************************************************************* + * + * Macros specific for Yukon-II queues + * + ******************************************************************************/ + +#define IS_Q_EMPTY(pQueue) ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE +#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock)) + +#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \ + if ((pQueue)->pHead != NULL) { \ + (pPacket) = (pQueue)->pHead; \ + (pQueue)->pHead = (pPacket)->pNext; \ + if ((pQueue)->pHead == NULL) { \ + (pQueue)->pTail = NULL; \ + } \ + (pPacket)->pNext = NULL; \ + } else { \ + (pPacket) = NULL; \ + } \ +} + +#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \ + if ((pQueue)->pHead != NULL) { \ + (pPacket)->pNext = (pQueue)->pHead; \ + } else { \ + (pPacket)->pNext = NULL; \ + (pQueue)->pTail = (pPacket); \ + } \ + (pQueue)->pHead = (pPacket); \ +} + +#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \ + (pPacket)->pNext = NULL; \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPacket); \ + } else { \ + (pQueue)->pHead = (pPacket); \ + } \ + (pQueue)->pTail = (pPacket); \ +} + +#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \ + if ((pPktGrpStart) != NULL) { \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPktGrpStart); \ + } else { \ + (pQueue)->pHead = (pPktGrpStart); \ + } \ + (pQueue)->pTail = (pPktGrpEnd); \ + } \ +} + +/* Required: 'Flags' */ +#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \ + spin_lock_irqsave(&((pQueue)->QueueLock), Flags); \ + if ((pQueue)->pHead != NULL) { \ + (pPacket) = (pQueue)->pHead; \ + (pQueue)->pHead = (pPacket)->pNext; \ + if ((pQueue)->pHead == NULL) { \ + (pQueue)->pTail = NULL; \ + } \ + (pPacket)->pNext = NULL; \ + } else { \ + (pPacket) = NULL; \ + } \ + spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags); \ +} + +/* Required: 'Flags' */ +#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \ + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \ + if ((pQueue)->pHead != NULL) { \ + (pPacket)->pNext = (pQueue)->pHead; \ + } else { \ + (pPacket)->pNext = NULL; \ + (pQueue)->pTail = (pPacket); \ + } \ + (pQueue)->pHead = (pPacket); \ + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \ +} + +/* Required: 'Flags' */ +#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \ + (pPacket)->pNext = NULL; \ + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPacket); \ + } else { \ + (pQueue)->pHead = (pPacket); \ + } \ + (pQueue)->pTail = (pPacket); \ + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \ +} + +/* Required: 'Flags' */ +#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \ + if ((pPktGrpStart) != NULL) { \ + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPktGrpStart); \ + } else { \ + (pQueue)->pHead = (pPktGrpStart); \ + } \ + (pQueue)->pTail = (pPktGrpEnd); \ + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \ + } \ +} + +/******************************************************************************* + * + * Used interrupt bits in the interrupts source register + * + ******************************************************************************/ + +#define DRIVER_IRQS ((IS_IRQ_SW) | \ + (IS_R1_F) | (IS_R2_F) | \ + (IS_XS1_F) | (IS_XA1_F) | \ + (IS_XS2_F) | (IS_XA2_F)) + +#define TX_COMPL_IRQS ((IS_XS1_B) | (IS_XS1_F) | \ + (IS_XA1_B) | (IS_XA1_F) | \ + (IS_XS2_B) | (IS_XS2_F) | \ + (IS_XA2_B) | (IS_XA2_F)) + +#define NAPI_DRV_IRQS ((IS_R1_F) | (IS_R2_F) | \ + (IS_XS1_F) | (IS_XA1_F)| \ + (IS_XS2_F) | (IS_XA2_F)) + +#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK)) + +#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \ + (IS_EXT_REG) |(IS_TIMINT) | \ + (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \ + (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \ + (IS_MAC1) |(IS_LNK_SYNC_M1)| \ + (IS_MAC2) |(IS_LNK_SYNC_M2)| \ + (IS_R1_C) |(IS_R2_C) | \ + (IS_XS1_C) |(IS_XA1_C) | \ + (IS_XS2_C) |(IS_XA2_C)) + +#define Y2_SPECIAL_IRQS ((Y2_IS_HW_ERR) |(Y2_IS_ASF) | \ + (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT) | \ + (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \ + (Y2_IS_CHK_RX2) |(Y2_IS_CHK_TXS2) | \ + (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \ + (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1) | \ + (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1)) + +#define IRQ_MASK ((IS_IRQ_SW) | \ + (IS_R1_F) |(IS_R2_F) | \ + (IS_XS1_F) |(IS_XA1_F) | \ + (IS_XS2_F) |(IS_XA2_F) | \ + (IS_HW_ERR) |(IS_I2C_READY)| \ + (IS_EXT_REG) |(IS_TIMINT) | \ + (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \ + (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \ + (IS_MAC1) |(IS_MAC2) | \ + (IS_R1_C) |(IS_R2_C) | \ + (IS_XS1_C) |(IS_XA1_C) | \ + (IS_XS2_C) |(IS_XA2_C)) + +#define Y2_IRQ_MASK ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS)) + +#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */ +#define Y2_IRQ_HWE_MASK (Y2_HWE_ALL_MSK) /* enable all HW irqs */ typedef struct s_DevNet DEV_NET; struct s_DevNet { - struct proc_dir_entry *proc; - int PortNr; - int NetNr; - int Mtu; - int Up; - SK_AC *pAC; + struct proc_dir_entry *proc; + int PortNr; + int NetNr; + int Mtu; + int Up; + char InitialDevName[20]; + SK_AC *pAC; }; -typedef struct s_TxPort TX_PORT; +/******************************************************************************* + * + * Rx/Tx Port structures + * + ******************************************************************************/ -struct s_TxPort { - /* the transmit descriptor rings */ - caddr_t pTxDescrRing; /* descriptor area memory */ - SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ - TXD *pTxdRingHead; /* Head of Tx rings */ - TXD *pTxdRingTail; /* Tail of Tx rings */ - TXD *pTxdRingPrev; /* descriptor sent previously */ - int TxdRingFree; /* # of free entrys */ - spinlock_t TxDesRingLock; /* serialize descriptor accesses */ - caddr_t HwAddr; /* bmu registers address */ - int PortIndex; /* index number of port (0 or 1) */ +typedef struct s_TxPort TX_PORT; +struct s_TxPort { /* the transmit descriptor rings */ + caddr_t pTxDescrRing; /* descriptor area memory */ + SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ + TXD *pTxdRingHead; /* Head of Tx rings */ + TXD *pTxdRingTail; /* Tail of Tx rings */ + TXD *pTxdRingPrev; /* descriptor sent previously */ + int TxdRingPrevFree;/* previously # of free entrys */ + int TxdRingFree; /* # of free entrys */ + spinlock_t TxDesRingLock; /* serialize descriptor accesses */ + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ + SK_PACKET *TransmitPacketTable; + SK_LE_TABLE TxALET; /* tx (async) list element table */ + SK_LE_TABLE TxSLET; /* tx (sync) list element table */ + SK_PKT_QUEUE TxQ_free; + SK_PKT_QUEUE TxAQ_waiting; + SK_PKT_QUEUE TxSQ_waiting; + SK_PKT_QUEUE TxAQ_working; + SK_PKT_QUEUE TxSQ_working; }; -typedef struct s_RxPort RX_PORT; - -struct s_RxPort { - /* the receive descriptor rings */ - caddr_t pRxDescrRing; /* descriptor area memory */ - SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ - RXD *pRxdRingHead; /* Head of Rx rings */ - RXD *pRxdRingTail; /* Tail of Rx rings */ - RXD *pRxdRingPrev; /* descriptor given to BMU previously */ - int RxdRingFree; /* # of free entrys */ - spinlock_t RxDesRingLock; /* serialize descriptor accesses */ - int RxFillLimit; /* limit for buffers in ring */ - caddr_t HwAddr; /* bmu registers address */ - int PortIndex; /* index number of port (0 or 1) */ +typedef struct s_RxPort RX_PORT; +struct s_RxPort { /* the receive descriptor rings */ + caddr_t pRxDescrRing; /* descriptor area memory */ + SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ + RXD *pRxdRingHead; /* Head of Rx rings */ + RXD *pRxdRingTail; /* Tail of Rx rings */ + RXD *pRxdRingPrev; /* descr given to BMU previously */ + int RxdRingFree; /* # of free entrys */ + spinlock_t RxDesRingLock; /* serialize descriptor accesses */ + int RxFillLimit; /* limit for buffers in ring */ + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ + SK_BOOL UseRxCsum; /* use Rx checksumming (yes/no) */ + SK_PACKET *ReceivePacketTable; + SK_LE_TABLE RxLET; /* rx list element table */ + SK_PKT_QUEUE RxQ_working; + SK_PKT_QUEUE RxQ_waiting; }; -/* Definitions needed for interrupt moderation *******************************/ +/******************************************************************************* + * + * Interrupt masks used in combination with interrupt moderation + * + ******************************************************************************/ #define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F)) #define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F)) @@ -317,139 +558,135 @@ #define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY)) #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX)) -#define C_INT_MOD_NONE 1 -#define C_INT_MOD_STATIC 2 -#define C_INT_MOD_DYNAMIC 4 - -#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */ -#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */ - -#define C_INTS_PER_SEC_DEFAULT 2000 -#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */ -#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */ -#define C_INT_MOD_IPS_LOWER_RANGE 30 -#define C_INT_MOD_IPS_UPPER_RANGE 40000 - - -typedef struct s_DynIrqModInfo DIM_INFO; -struct s_DynIrqModInfo { - unsigned long PrevTimeVal; - unsigned int PrevSysLoad; - unsigned int PrevUsedTime; - unsigned int PrevTotalTime; - int PrevUsedDescrRatio; - int NbrProcessedDescr; - SK_U64 PrevPort0RxIntrCts; - SK_U64 PrevPort1RxIntrCts; - SK_U64 PrevPort0TxIntrCts; - SK_U64 PrevPort1TxIntrCts; - SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */ - - int MaxModIntsPerSec; /* Moderation Threshold */ - int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */ - int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */ - - long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */ - SK_BOOL DisplayStats; /* Stats yes/no */ - SK_BOOL AutoSizing; /* Resize DIM-timer on/off */ - int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */ +#define IRQ_MASK_Y2_TX_ONLY (Y2_IS_STAT_BMU) +#define IRQ_MASK_Y2_RX_ONLY (Y2_IS_STAT_BMU) +#define IRQ_MASK_Y2_SP_ONLY (SPECIAL_IRQS) +#define IRQ_MASK_Y2_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY)) +#define IRQ_MASK_Y2_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY)) +#define IRQ_MASK_Y2_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY)) +#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX)) - SK_TIMER ModTimer; /* just some timer */ -}; +/******************************************************************************* + * + * Defines and typedefs regarding interrupt moderation + * + ******************************************************************************/ -typedef struct s_PerStrm PER_STRM; +#define C_INT_MOD_NONE 1 +#define C_INT_MOD_STATIC 2 +#define C_INT_MOD_DYNAMIC 4 + +#define C_CLK_FREQ_GENESIS 53215000 /* or: 53.125 MHz */ +#define C_CLK_FREQ_YUKON 78215000 /* or: 78.125 MHz */ +#define C_CLK_FREQ_YUKON_EC 125000000 /* or: 125.000 MHz */ + +#define C_Y2_INTS_PER_SEC_DEFAULT 5000 +#define C_INTS_PER_SEC_DEFAULT 2000 +#define C_INT_MOD_IPS_LOWER_RANGE 30 /* in IRQs/second */ +#define C_INT_MOD_IPS_UPPER_RANGE 40000 /* in IRQs/second */ + +typedef struct s_DynIrqModInfo { + SK_U64 PrevPort0RxIntrCts; + SK_U64 PrevPort1RxIntrCts; + SK_U64 PrevPort0TxIntrCts; + SK_U64 PrevPort1TxIntrCts; + SK_U64 PrevPort0StatusLeIntrCts; + SK_U64 PrevPort1StatusLeIntrCts; + int MaxModIntsPerSec; /* Moderation Threshold */ + int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */ + int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */ + long MaskIrqModeration; /* IRQ Mask (eg. 'TxRx') */ + int IntModTypeSelect; /* Type (eg. 'dynamic') */ + int DynIrqModSampleInterval; /* expressed in seconds! */ + SK_TIMER ModTimer; /* Timer for dynamic mod. */ +} DIM_INFO; #define SK_ALLOC_IRQ 0x00000001 - -#ifdef SK_DIAG_SUPPORT #define DIAG_ACTIVE 1 #define DIAG_NOTACTIVE 0 -#endif /**************************************************************************** + * * Per board structure / Adapter Context structure: - * Allocated within attach(9e) and freed within detach(9e). - * Contains all 'per device' necessary handles, flags, locks etc.: - */ -struct s_AC { - SK_GEINIT GIni; /* GE init struct */ - SK_PNMI Pnmi; /* PNMI data struct */ - SK_VPD vpd; /* vpd data struct */ - SK_QUEUE Event; /* Event queue */ - SK_HWT Hwt; /* Hardware Timer control struct */ - SK_TIMCTRL Tim; /* Software Timer control struct */ - SK_I2C I2c; /* I2C relevant data structure */ - SK_ADDR Addr; /* for Address module */ - SK_CSUM Csum; /* for checksum module */ - SK_RLMT Rlmt; /* for rlmt module */ - spinlock_t SlowPathLock; /* Normal IRQ lock */ - SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */ - int RlmtMode; /* link check mode to set */ - int RlmtNets; /* Number of nets */ - - SK_IOC IoBase; /* register set of adapter */ - int BoardLevel; /* level of active hw init (0-2) */ - char DeviceStr[80]; /* adapter string from vpd */ - SK_U32 AllocFlag; /* flag allocation of resources */ - struct pci_dev *PciDev; /* for access to pci config space */ - SK_U32 PciDevId; /* pci device id */ - struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ - char Name[30]; /* driver name */ - struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */ - int RxBufSize; /* length of receive buffers */ - struct net_device_stats stats; /* linux 'netstat -i' statistics */ - int Index; /* internal board index number */ - - /* adapter RAM sizes for queues of active port */ - int RxQueueSize; /* memory used for receive queue */ - int TxSQueueSize; /* memory used for sync. tx queue */ - int TxAQueueSize; /* memory used for async. tx queue */ - - int PromiscCount; /* promiscuous mode counter */ - int AllMultiCount; /* allmulticast mode counter */ - int MulticCount; /* number of different MC */ - /* addresses for this board */ - /* (may be more than HW can)*/ - - int HWRevision; /* Hardware revision */ - int ActivePort; /* the active XMAC port */ - int MaxPorts; /* number of activated ports */ - int TxDescrPerRing; /* # of descriptors per tx ring */ - int RxDescrPerRing; /* # of descriptors per rx ring */ - - caddr_t pDescrMem; /* Pointer to the descriptor area */ - dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ - - /* the port structures with descriptor rings */ - TX_PORT TxPort[SK_MAX_MACS][2]; - RX_PORT RxPort[SK_MAX_MACS]; - - unsigned int CsOfs1; /* for checksum calculation */ - unsigned int CsOfs2; /* for checksum calculation */ - SK_U32 CsOfs; /* for checksum calculation */ - - SK_BOOL CheckQueue; /* check event queue soon */ - SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */ - DIM_INFO DynIrqModInfo; /* all data related to DIM */ - - /* Only for tests */ - int PortUp; - int PortDown; - int ChipsetType; /* Chipset family type - * 0 == Genesis family support - * 1 == Yukon family support - */ -#ifdef SK_DIAG_SUPPORT - SK_U32 DiagModeActive; /* is diag active? */ - SK_BOOL DiagFlowCtrl; /* for control purposes */ - SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */ - SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while - * DIAG is busy with NIC - */ -#endif + * Contains all 'per device' necessary handles, flags, locks etc.: + * + ******************************************************************************/ +struct s_AC { + SK_GEINIT GIni; /* GE init struct */ + SK_PNMI Pnmi; /* PNMI data struct */ + SK_VPD vpd; /* vpd data struct */ + SK_QUEUE Event; /* Event queue */ + SK_HWT Hwt; /* Hardware Timer ctrl struct */ + SK_TIMCTRL Tim; /* Software Timer ctrl struct */ + SK_I2C I2c; /* I2C relevant data structure*/ + SK_ADDR Addr; /* for Address module */ + SK_CSUM Csum; /* for checksum module */ + SK_RLMT Rlmt; /* for rlmt module */ + spinlock_t SlowPathLock; /* Normal IRQ lock */ + SK_PNMI_STRUCT_DATA PnmiStruct; /* struct for all Pnmi-Data */ + int RlmtMode; /* link check mode to set */ + int RlmtNets; /* Number of nets */ + SK_IOC IoBase; /* register set of adapter */ + int BoardLevel; /* level of hw init (0-2) */ + char DeviceStr[80]; /* adapter string from vpd */ + SK_U32 AllocFlag; /* alloc flag of resources */ + struct pci_dev *PciDev; /* for access to pci cfg space*/ + SK_U32 PciDevId; /* pci device id */ + struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ + char Name[30]; /* driver name */ + struct SK_NET_DEVICE *Next; /* link all devs for cleanup */ + int RxBufSize; /* length of receive buffers */ + struct net_device_stats stats; /* linux 'netstat -i' stats */ + int Index; /* internal board idx number */ + int RxQueueSize; /* memory used for RX queue */ + int TxSQueueSize; /* memory used for TXS queue */ + int TxAQueueSize; /* memory used for TXA queue */ + int PromiscCount; /* promiscuous mode counter */ + int AllMultiCount; /* allmulticast mode counter */ + int MulticCount; /* number of MC addresses used*/ + int HWRevision; /* Hardware revision */ + int ActivePort; /* the active XMAC port */ + int MaxPorts; /* number of activated ports */ + int TxDescrPerRing;/* # of descriptors TX ring */ + int RxDescrPerRing;/* # of descriptors RX ring */ + caddr_t pDescrMem; /* Ptr to the descriptor area */ + dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ + TX_PORT TxPort[SK_MAX_MACS][2]; + RX_PORT RxPort[SK_MAX_MACS]; + SK_LE_TABLE TxListElement[SK_MAX_MACS][2]; + SK_LE_TABLE RxListElement[SK_MAX_MACS]; + SK_LE_TABLE StatusLETable; + unsigned SizeOfAlignedLETables; + spinlock_t SetPutIndexLock; + int MaxUnusedRxLeWorking; + unsigned int CsOfs1; /* for checksum calculation */ + unsigned int CsOfs2; /* for checksum calculation */ + SK_U32 CsOfs; /* for checksum calculation */ + SK_BOOL CheckQueue; /* check event queue soon */ + DIM_INFO DynIrqModInfo; /* all data related to IM */ + int PortUp; + int PortDown; + int ChipsetType; /* 0=GENESIS; 1=Yukon */ + SK_U32 DiagModeActive;/* is diag active? */ + SK_BOOL DiagFlowCtrl; /* for control purposes */ + SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for PNMI */ + SK_BOOL WasIfUp[SK_MAX_MACS]; }; -#endif /* __INC_SKDRV2ND_H */ +/******************************************************************************* + * + * Defines and typedefs regarding power management + * + ******************************************************************************/ + +/* Disabled at the moment */ + +#endif +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h --- linux/drivers/net/sk98lin/h/skerror.h 2004-08-14 12:55:32.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skerror.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skerror.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.7 $ - * Date: $Date: 2003/05/13 17:25:13 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2004/05/24 15:27:19 $ * Purpose: SK specific Error log support * ******************************************************************************/ @@ -11,13 +11,12 @@ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -36,7 +35,6 @@ #define SK_ERRCL_HW (1L<<4) /* Hardware Failure */ #define SK_ERRCL_COMM (1L<<5) /* Communication error */ - /* * Define Error Code Bases */ @@ -49,7 +47,9 @@ #define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */ #define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */ #define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */ -#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */ +#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */ #define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */ +#define SK_ERRBASE_ASF 1200 /* Base Error number for ASF */ #endif /* _INC_SKERROR_H_ */ + diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h --- linux/drivers/net/sk98lin/h/skgedrv.h 2004-08-14 12:55:35.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgedrv.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skgedrv.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.10 $ - * Date: $Date: 2003/07/04 12:25:01 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:08 $ * Purpose: Interface with the driver * ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h --- linux/drivers/net/sk98lin/h/skgehw.h 2004-08-14 12:56:23.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgehw.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skgehw.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.56 $ - * Date: $Date: 2003/09/23 09:01:00 $ + * Version: $Revision: 2.42 $ + * Date: $Date: 2004/08/13 09:21:20 $ * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family * ******************************************************************************/ @@ -11,13 +11,12 @@ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -114,6 +113,16 @@ #define SHIFT1(x) ((x) << 1) #define SHIFT0(x) ((x) << 0) +/* Macro for arbitrary alignment of a given pointer */ +#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \ + SK_UPTR addr = (SK_UPTR)(ADDRESS); \ + if (addr & ((GRANULARITY)-1)) { \ + addr += (GRANULARITY); \ + addr &= ~(SK_UPTR)((GRANULARITY)-1); \ + ADDRESS = (void *)addr; \ + }\ +} + /* * Configuration Space header * Since this module is used for different OS', those may be @@ -132,12 +141,12 @@ #define PCI_BIST 0x0f /* 8 bit Built-in selftest */ #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ - /* Byte 0x18..0x2b: reserved */ + /* Bytes 0x18..0x2b: reserved */ #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ #define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */ - /* Byte 0x35..0x3b: reserved */ + /* Bytes 0x35..0x3b: reserved */ #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ @@ -147,19 +156,59 @@ #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ /* Power Management Region */ #define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ -#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */ +#define PCI_PM_NITEM 0x49 /* 8 bit PM Next Item Pointer */ #define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ #define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ /* Byte 0x4e: reserved */ #define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ /* VPD Region */ #define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ -#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */ +#define PCI_VPD_NITEM 0x51 /* 8 bit VPD Next Item Pointer */ #define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ #define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ - /* Byte 0x58..0x59: reserved */ + /* Bytes 0x58..0x59: reserved */ #define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */ - /* Byte 0x5c..0xff: reserved */ + /* Bytes 0x5c..0xfc: used by Yukon-2 */ +#define PCI_MSI_CAP_ID 0x5c /* 8 bit MSI Capability ID Register */ +#define PCI_MSI_NITEM 0x5d /* 8 bit MSI Next Item Pointer */ +#define PCI_MSI_CTRL 0x5e /* 16 bit MSI Message Control */ +#define PCI_MSI_ADR_LO 0x60 /* 32 bit MSI Message Address (Lower) */ +#define PCI_MSI_ADR_HI 0x64 /* 32 bit MSI Message Address (Upper) */ +#define PCI_MSI_DATA 0x68 /* 16 bit MSI Message Data */ + /* Bytes 0x6a..0x6b: reserved */ +#define PCI_X_CAP_ID 0x6c /* 8 bit PCI-X Capability ID Register */ +#define PCI_X_NITEM 0x6d /* 8 bit PCI-X Next Item Pointer */ +#define PCI_X_COMMAND 0x6e /* 16 bit PCI-X Command */ +#define PCI_X_PE_STAT 0x70 /* 32 bit PCI-X / PE Status */ +#define PCI_CAL_CTRL 0x74 /* 16 bit PCI Calibration Control Register */ +#define PCI_CAL_STAT 0x76 /* 16 bit PCI Calibration Status Register */ +#define PCI_DISC_CNT 0x78 /* 16 bit PCI Discard Counter */ +#define PCI_RETRY_CNT 0x7a /* 8 bit PCI Retry Counter */ + /* Byte 0x7b: reserved */ +#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ + /* Bytes 0x80..0xdf: reserved */ + +/* PCI Express Capability */ +#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ +#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ +#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ +#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ +#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ +#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ +#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ +#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ +#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ + /* Bytes 0xf4..0xff: reserved */ + +/* PCI Express Extended Capabilities */ +#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ +#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ +#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ +#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ +#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ +#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ +#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ +#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ /* * I2C Address (PCI Config) @@ -180,7 +229,7 @@ #define PCI_ADSTEP BIT_7S /* Address Stepping */ #define PCI_PERREN BIT_6S /* Parity Report Response enable */ #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */ -#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */ +#define PCI_MWIEN BIT_4S /* Memory write an inv cycl enable */ #define PCI_SCYCEN BIT_3S /* Special Cycle enable */ #define PCI_BMEN BIT_2S /* Bus Master enable */ #define PCI_MEMEN BIT_1S /* Memory Space Access enable */ @@ -229,33 +278,42 @@ #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */ #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */ #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */ -#define PCI_PREFEN BIT_3 /* Prefetchable */ -#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */ +#define PCI_PREFEN BIT_3 /* Prefetch enable */ +#define PCI_MEM_TYP_MSK (3L<<1) /* Bit 2.. 1: Memory Type Mask */ +#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */ + #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */ #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */ #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */ -#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */ /* PCI_BASE_2ND 32 bit 2nd Base address */ #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */ #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */ - /* Bit 1: reserved */ + /* Bit 1: reserved */ #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */ /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ #define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */ #define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */ #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */ - /* Bit 10.. 1: reserved */ + /* Bit 10.. 1: reserved */ #define PCI_ROMEN BIT_0 /* Address Decode enable */ /* Device Dependent Region */ /* PCI_OUR_REG_1 32 bit Our Register 1 */ - /* Bit 31..29: reserved */ + /* Bit 31..29: reserved */ #define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */ #define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */ #define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */ #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */ +/* Yukon-2 */ +#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ +#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ +#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ +#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ +#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ +#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ + /* Bit 25: reserved */ #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ #define PCI_EN_IO BIT_23 /* Mapping to I/O space */ #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ @@ -266,9 +324,10 @@ #define PCI_PAGE_32K (1L<<20) /* 32 k pages */ #define PCI_PAGE_64K (2L<<20) /* 64 k pages */ #define PCI_PAGE_128K (3L<<20) /* 128 k pages */ - /* Bit 19: reserved */ + /* Bit 19: reserved */ #define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ #define PCI_NOTAR BIT_15 /* No turnaround cycle */ +#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ @@ -279,12 +338,11 @@ #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */ #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ - /* PCI_OUR_REG_2 32 bit Our Register 2 */ #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */ #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */ #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */ - /* Bit 13..12: reserved */ + /* Bit 13..12: reserved */ #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ #define PCI_PATCH_DIR_3 BIT_11 #define PCI_PATCH_DIR_2 BIT_10 @@ -297,21 +355,20 @@ #define PCI_EXT_PATCH_0 BIT_4 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ - /* Bit 1: reserved */ + /* Bit 1: reserved */ #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ - /* Power Management Region */ /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */ #define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */ -#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */ +#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if VAUX) */ #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */ #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */ #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */ #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */ #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */ #define PCI_PM_D1_SUP BIT_9S /* D1 Support */ - /* Bit 8.. 6: reserved */ + /* Bit 8.. 6: reserved */ #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */ #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */ #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */ @@ -322,7 +379,7 @@ #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */ #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */ #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */ - /* Bit 7.. 2: reserved */ + /* Bit 7.. 2: reserved */ #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */ #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */ @@ -333,7 +390,59 @@ /* VPD Region */ /* PCI_VPD_ADR_REG 16 bit VPD Address Register */ #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */ -#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */ +#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD Address Mask */ + +/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ +#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ +#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ +#define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ +#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ +#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ +#define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ +#define PCI_OS_DLLR_MSK (0xf<<20) /* Bit 23..20: DLL Row Counters Values */ +#define PCI_OS_DLLC_MSK (0xf<<16) /* Bit 19..16: DLL Col. Counters Values */ + /* Bit 15.. 8: reserved */ + +#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ +/* possible values for the speed field of the register */ +#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ +#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ +#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ +#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ + +/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ + /* Bit 15 reserved */ +#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ +#define PEX_DC_EN_NO_SNOOP BIT_11S /* Enable No Snoop */ +#define PEX_DC_EN_AUX_POW BIT_10S /* Enable AUX Power */ +#define PEX_DC_EN_PHANTOM BIT_9S /* Enable Phantom Functions */ +#define PEX_DC_EN_EXT_TAG BIT_8S /* Enable Extended Tag Field */ +#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ +#define PEX_DC_EN_REL_ORD BIT_4S /* Enable Relaxed Ordering */ +#define PEX_DC_EN_UNS_RQ_RP BIT_3S /* Enable Unsupported Request Reporting */ +#define PEX_DC_EN_FAT_ER_RP BIT_2S /* Enable Fatal Error Reporting */ +#define PEX_DC_EN_NFA_ER_RP BIT_1S /* Enable Non-Fatal Error Reporting */ +#define PEX_DC_EN_COR_ER_RP BIT_0S /* Enable Correctable Error Reporting */ + +#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) + +/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ + /* Bit 31..21 reserved */ +#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ + /* ECRC Error (not supported) */ +#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ + /* Receiver Overflow (not supported) */ +#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ + /* Completer Abort (not supported) */ +#define PEX_COMP_TO BIT_14 /* Completion Timeout */ +#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ +#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ + /* Bit 11.. 5: reserved */ +#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ + /* Bit 3.. 1: reserved */ + /* Training Error (not supported) */ + +#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) /* Control Register File (Address Map) */ @@ -349,8 +458,14 @@ #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ -#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */ - /* 0x001c: reserved */ +#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ + +/* Special ISR registers (Yukon-2 only) */ +#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ +#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ +#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ +#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ +#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ /* B0 XMAC 1 registers (GENESIS only) */ #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/ @@ -401,13 +516,22 @@ #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ - /* Eprom registers are currently of no use */ + /* Eprom registers */ #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ +/* Yukon and Genesis */ #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */ #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */ +/* Yukon-2 */ +#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ +#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ + #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ + +/* Yukon and Genesis */ #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */ #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */ +/* Yukon-2 */ +#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ /* 0x0125 - 0x0127: reserved */ #define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */ #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */ @@ -439,6 +563,10 @@ #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */ #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */ #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */ + +/* Yukon-2 */ +#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ +#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ /* 0x017c - 0x017f: reserved */ /* @@ -448,9 +576,13 @@ #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ - /* 0x018c - 0x018f: reserved */ + +#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ + + /* 0x018c - 0x018f: reserved */ /* RAM Interface Registers */ +/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ /* * The HW-Spec. calls this registers Timeout Value 0..11. But this names are * not usable in SW. Please notice these are NOT real timeouts, these are @@ -517,8 +649,8 @@ /* 0x01ea - 0x01eb: reserved */ #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */ /* 0x01ee - 0x01ef: reserved */ -#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */ -#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */ +#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */ +#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */ /* 0x01f4 - 0x01ff: reserved */ /* @@ -532,7 +664,16 @@ #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ - /* 0x0213 - 0x027f: reserved */ + /* 0x0213 - 0x021f: reserved */ + + /* RSS key registers for Yukon-2 Family */ +#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ + /* RSS key register offsets */ +#define KEY_IDX_0 0 /* offset for location of KEY 0 */ +#define KEY_IDX_1 4 /* offset for location of KEY 1 */ +#define KEY_IDX_2 8 /* offset for location of KEY 2 */ +#define KEY_IDX_3 12 /* offset for location of KEY 3 */ + /* 0x0280 - 0x0292: MAC 2 */ /* 0x0213 - 0x027f: reserved */ @@ -570,8 +711,37 @@ #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ #define Q_T2 0x40 /* 32 bit Test Register 2 */ #define Q_T3 0x44 /* 32 bit Test Register 3 */ + +/* Yukon-2 */ +#define Q_DONE 0x24 /* 16 bit Done Index (Yukon-2 only) */ +#define Q_WM 0x40 /* 16 bit FIFO Watermark */ +#define Q_AL 0x42 /* 8 bit FIFO Alignment */ +#define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ +#define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ +#define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ +#define Q_RL 0x4a /* 8 bit FIFO Read Level */ +#define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ +#define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ +#define Q_WL 0x4e /* 8 bit FIFO Write Level */ +#define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ /* 0x48 - 0x7f: reserved */ +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ +#define Y2_B8_PREF_REGS 0x0450 + +#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ +#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ +#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ +#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ +#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ +#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ +#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ +#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ +#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ +#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ + +#define PREF_UNIT_MASK_IDX 0x0fff + /* * Bank 16 - 23 */ @@ -583,17 +753,17 @@ #define RB_END 0x04 /* 32 bit RAM Buffer End Address */ #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ -#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */ -#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */ +#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ +#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ -#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ +#define RB_CTRL 0x28 /* 32 bit RAM Buffer Control Register */ #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ -#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */ - /* 0x2c - 0x7f: reserved */ +#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ + /* 0x2b - 0x7f: reserved */ /* * Bank 24 @@ -628,13 +798,15 @@ #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */ /* 0x0c3d - 0x0c3f: reserved */ -/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */ +/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ - /* 0x0c54 - 0x0c5f: reserved */ +#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ + /* 0x0c58 - 0x0c5b: reserved */ +#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ /* 0x0c64 - 0x0c67: reserved */ #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ @@ -676,11 +848,12 @@ #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */ /* 0x0d2a - 0x0d3f: reserved */ -/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */ +/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ - /* 0x0d4c - 0x0d5f: reserved */ + /* 0x0d4c - 0x0d5b: reserved */ +#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ @@ -713,12 +886,84 @@ #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ /* 0x0e19: reserved */ #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ - /* 0x0e1b - 0x0e7f: reserved */ + /* 0x0e1b - 0x0e1f: reserved */ + +/* Polling Unit Registers (Yukon-2 only) */ +#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ +#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ + /* 0x0e26 - 0x0e27: reserved */ +#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ +#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ + /* 0x0e30 - 0x0e3f: reserved */ + +/* ASF Subsystem Registers (Yukon-2 only) */ +#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ +#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ + /* 0x0e48 - 0x0e5f: reserved */ +#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ + /* 0x0e64 - 0x0e67: reserved */ +#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ +#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ +#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ +#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ +#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ +#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ /* * Bank 29 */ - /* 0x0e80 - 0x0efc: reserved */ + +/* Status BMU Registers (Yukon-2 only)*/ +#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ +#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ + /* 0x0e85 - 0x0e86: reserved */ +#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ +#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ +#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ +#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ +#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ +#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ +#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ + /* 0x0e9a - 0x0e9b: reserved */ +#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ + /* 0x0e9e - 0x0e9f: reserved */ + +/* FIFO Control/Status Registers (Yukon-2 only)*/ +#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ + /* 0x0ea1 - 0x0ea3: reserved */ +#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ + /* 0x0ea5: reserved */ +#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ + /* 0x0ea7: reserved */ +#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ + /* 0x0ea9: reserved */ +#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ + /* 0x0eab: reserved */ +#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ +#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ + /* 0x0eae - 0x0eaf: reserved */ + +/* Level and ISR Timer Registers (Yukon-2 only)*/ +#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ +#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ +#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ +#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ + /* 0x0eba - 0x0ebf: reserved */ +#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ +#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ +#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ +#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ + /* 0x0eca - 0x0ecf: reserved */ +#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ +#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ +#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ +#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ + /* 0x0eda - 0x0eff: reserved */ + +#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ +#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ +#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ +#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ /* * Bank 30 @@ -742,11 +987,9 @@ #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ -#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */ - -/* use this macro to access above registers */ -#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs)) - +#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ +#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ +#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ /* WOL Pattern Length Registers (YUKON only) */ @@ -764,11 +1007,22 @@ */ /* 0x0f80 - 0x0fff: reserved */ +/* WOL registers link 2 */ + +/* use this macro to access WOL registers */ +#define WOL_REG(Port, Reg) ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs)) + /* * Bank 32 - 33 */ #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ +#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ + +/* use this macro to retrieve the pattern ram base address */ +#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400) +/* offset to configuration space on Yukon-2 */ +#define Y2_CFG_SPC 0x1c00 /* * Bank 0x22 - 0x3f */ @@ -802,11 +1056,24 @@ /* Bit 7: reserved */ #define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */ +/* B0_CTST 24 bit Control/Status register */ + /* Bit 23..18: reserved */ +#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ +#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ + /* Bit 15..14: reserved */ +#define Y2_ASF_ENABLE BIT_13S /* ASF Unit Enable (YUKON-2 only) */ +#define Y2_ASF_DISABLE BIT_12S /* ASF Unit Disable (YUKON-2 only) */ +#define Y2_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-2 only) */ +#define Y2_CLK_RUN_DIS BIT_10S /* CLK_RUN Disable (YUKON-2 only) */ +#define Y2_LED_STAT_ON BIT_9S /* Status LED On (YUKON-2 only) */ +#define Y2_LED_STAT_OFF BIT_8S /* Status LED Off (YUKON-2 only) */ + /* Bit 7.. 0: same as below */ + /* B0_CTST 16 bit Control/Status register */ /* Bit 15..14: reserved */ -#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */ -#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */ -#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */ +#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN Hot m. (YUKON-Lite only) */ +#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN Reset (YUKON-Lite only) */ +#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-Lite only) */ #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */ #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */ #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */ @@ -814,15 +1081,15 @@ #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */ #define CS_STOP_DONE BIT_5S /* Stop Master is finished */ #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */ -#define CS_MRST_CLR BIT_3S /* Clear Master reset */ -#define CS_MRST_SET BIT_2S /* Set Master reset */ -#define CS_RST_CLR BIT_1S /* Clear Software reset */ -#define CS_RST_SET BIT_0S /* Set Software reset */ +#define CS_MRST_CLR BIT_3S /* Clear Master Reset */ +#define CS_MRST_SET BIT_2S /* Set Master Reset */ +#define CS_RST_CLR BIT_1S /* Clear Software Reset */ +#define CS_RST_SET BIT_0S /* Set Software Reset */ -/* B0_LED 8 Bit LED register */ +/* B0_LED 8 Bit LED register (GENESIS only)*/ /* Bit 7.. 2: reserved */ -#define LED_STAT_ON BIT_1S /* Status LED on */ -#define LED_STAT_OFF BIT_0S /* Status LED off */ +#define LED_STAT_ON BIT_1S /* Status LED On */ +#define LED_STAT_OFF BIT_0S /* Status LED Off */ /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ @@ -834,6 +1101,7 @@ #define PC_VCC_ON BIT_1 /* Switch VCC On */ #define PC_VCC_OFF BIT_0 /* Switch VCC Off */ +/* Yukon and Genesis */ /* B0_ISRC 32 bit Interrupt Source Register */ /* B0_IMSK 32 bit Interrupt Mask Register */ /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ @@ -879,12 +1147,51 @@ #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */ #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */ +/* (Yukon-2) */ +/* B0_ISRC 32 bit Interrupt Source Register */ +/* B0_IMSK 32 bit Interrupt Mask Register */ +/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ +#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) +#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ +#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ +#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ + /* Bit 28: reserved */ +#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ +#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ +#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ +#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ + /* Bit 23..16 reserved */ + /* Link 2 Interrupts */ +#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ +#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ +#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ +#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ +#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ + /* Bit 7.. 5 reserved */ + /* Link 1 interrupts */ +#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ +#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ +#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ +#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ +#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ + +#define Y2_IS_L1_MASK 0x0000001fUL /* IRQ Mask for port 1 */ +#define Y2_IS_L2_MASK 0x00001f00UL /* IRQ Mask for port 2 */ + +#define Y2_IS_ALL_MSK 0xef001f1fUL /* All Interrupt bits */ + +/* Yukon and Genesis */ /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ #define IS_ERR_MSK 0x00000fffL /* All Error bits */ - /* Bit 31..14: reserved */ + /* Bit 31..14: reserved */ #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */ #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */ #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */ @@ -900,6 +1207,43 @@ #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */ #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */ + /* Yukon-2 */ +/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ +/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ + /* Bit: 31..30 reserved */ +#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ +#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ +#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ +#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ +#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ +#define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ + /* Bit: 23..14 reserved */ + /* Link 2 */ +#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ +#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ +#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ +#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ +#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ +#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ + /* Bit: 9.. 6 reserved */ + /* Link 1 */ +#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ +#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ +#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ +#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ +#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ +#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ + +#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) +#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) + +#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ + Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) + /* B2_CONN_TYP 8 bit Connector type */ /* B2_PMD_TYP 8 bit PMD type */ /* Values of connector and PMD type comply to SysKonnect internal std */ @@ -908,19 +1252,64 @@ #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ /* Bit 3.. 2: reserved */ #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ -#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ +#define CFG_SNG_MAC BIT_0S /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ /* B2_CHIP_ID 8 bit Chip Identification Number */ #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ +#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ +#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ +#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */ #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */ +#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ +#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ + +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ +#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */ +#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable clock gating Link 2 */ +#define Y2_COR_CLK_LNK2_DIS BIT_5S /* Disable Core clock Link 2 */ +#define Y2_PCI_CLK_LNK2_DIS BIT_4S /* Disable PCI clock Link 2 */ +#define Y2_STATUS_LNK1_INAC BIT_3S /* Status Link 1 inactiv (0 = activ) */ +#define Y2_CLK_GAT_LNK1_DIS BIT_2S /* Disable clock gating Link 1 */ +#define Y2_COR_CLK_LNK1_DIS BIT_1S /* Disable Core clock Link 1 */ +#define Y2_PCI_CLK_LNK1_DIS BIT_0S /* Disable PCI clock Link 1 */ + +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ + /* Bit 7.. 5: reserved */ +#define CFG_LED_MODE_MSK (7<<2) /* Bit 4.. 2: LED Mode Mask */ +#define CFG_LINK_2_AVAIL BIT_1S /* Link 2 available */ +#define CFG_LINK_1_AVAIL BIT_0S /* Link 1 available */ + +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) + +#define CFG_LED_SING_ACT_LNK 0 /* Single LED ACT/LNK mode */ +#define CFG_LED_DUAL_ACT_LNK 1 /* Dual LED ACT/LNK mode */ + +/* B2_E_3 8 bit lower 4 bits used for HW self test result */ +#define B2_E3_RES_MASK 0x0f + /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */ -#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */ +#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address Mask */ + +/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ + /* Bit 31..24: reserved */ +/* Yukon-EC/FE */ +#define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ +#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) +/* Yukon-2 */ +#define Y2_CLK_DIV_VAL2_MSK (7<<21) /* Bit 23..21: Clock Divisor Value */ +#define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ +#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) +#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT_MSK) + /* Bit 15.. 2: reserved */ +#define Y2_CLK_DIV_ENA BIT_1S /* Enable Core Clock Division */ +#define Y2_CLK_DIV_DIS BIT_0S /* Disable Core Clock Division */ /* B2_LD_CTRL 8 bit EPROM loader control register */ /* Bits are currently reserved */ @@ -960,9 +1349,6 @@ #define DPT_START BIT_1S /* Start Descriptor Poll Timer */ #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */ -/* B2_E_3 8 bit lower 4 bits used for HW self test result */ -#define B2_E3_RES_MASK 0x0f - /* B2_TST_CTRL1 8 bit Test Control Register 1 */ #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */ #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */ @@ -982,7 +1368,7 @@ #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */ /* B2_GP_IO 32 bit General Purpose I/O Register */ - /* Bit 31..26: reserved */ + /* Bit 31..26: reserved */ #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */ #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */ #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */ @@ -1032,10 +1418,8 @@ #define I2C_DATA BIT_1S /* I2C Data Port */ #define I2C_CLK BIT_0S /* I2C Clock Port */ -/* - * I2C Address - */ -#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/ +/* I2C Address */ +#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ @@ -1052,16 +1436,20 @@ #define BSC_T_OFF BIT_1S /* Test mode off */ #define BSC_T_STEP BIT_0S /* Test step */ +/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ +#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ +#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ + /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ /* Bit 31..19: reserved */ #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ /* RAM Interface Registers */ -/* B3_RI_CTRL 16 bit RAM Iface Control Register */ +/* B3_RI_CTRL 16 bit RAM Interface Control Register */ /* Bit 15..10: reserved */ -#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */ -#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/ +#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */ +#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err */ /* Bit 7.. 2: reserved */ #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */ #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */ @@ -1171,7 +1559,7 @@ /* Bit 31..16: reserved */ #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ -/* BMU Control Status Registers */ +/* BMU Control / Status Registers (Yukon and Genesis) */ /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ @@ -1212,6 +1600,42 @@ CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ CSR_TRANS_RUN) +/* Rx BMU Control / Status Registers (Yukon-2) */ +#define BMU_IDLE BIT_31 /* BMU Idle State */ +#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ +#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ + /* Bit 28..16: reserved */ +#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ +#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ +#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ +#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ +#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ +#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ + +#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ +#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ +#define BMU_START BIT_8 /* Start Rx/Tx Queue */ +#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ +#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ +#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ +#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ +#define BMU_OP_ON BIT_3 /* BMU Operational On */ +#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ +#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ +#define BMU_RST_SET BIT_0 /* Set BMU Reset */ + +#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) +#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \ + BMU_FIFO_ENA | BMU_OP_ON) + +/* Tx BMU Control / Status Registers (Yukon-2) */ + /* Bit 31: same as for Rx */ + /* Bit 30..14: reserved */ +#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ +#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ +#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ + /* Bit 10..0: same as for Rx */ + /* Q_F 32 bit Flag Register */ /* Bit 31..28: reserved */ #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */ @@ -1260,6 +1684,13 @@ /* Bit 3: reserved */ #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */ +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ +/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ +#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ +#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ +#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ +#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ + /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ /* RB_START 32 bit RAM Buffer Start Address */ /* RB_END 32 bit RAM Buffer End Address */ @@ -1275,24 +1706,24 @@ #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ /* RB_TST2 8 bit RAM Buffer Test Register 2 */ - /* Bit 7.. 4: reserved */ -#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */ + /* Bit 7.. 4: reserved */ +#define RB_PC_DEC BIT_3S /* Packet Counter Decrement */ #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */ -#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */ -#define RB_PC_INC BIT_0S /* Packet Counter Increm */ +#define RB_PC_T_OFF BIT_1S /* Packet Counter Test Off */ +#define RB_PC_INC BIT_0S /* Packet Counter Increment */ /* RB_TST1 8 bit RAM Buffer Test Register 1 */ /* Bit 7: reserved */ #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */ #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */ -#define RB_WP_INC BIT_4S /* Write Pointer Increm */ +#define RB_WP_INC BIT_4S /* Write Pointer Increment */ /* Bit 3: reserved */ #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */ #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */ -#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */ +#define RB_RP_INC BIT_0S /* Read Pointer Increment */ /* RB_CTRL 8 bit RAM Buffer Control Register */ - /* Bit 7.. 6: reserved */ + /* Bit 7.. 6: reserved */ #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */ #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */ #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */ @@ -1300,6 +1731,21 @@ #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */ #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */ +/* Yukon-2 */ + /* Bit 31..20: reserved */ +#define RB_CNT_DOWN BIT_19 /* Packet Counter Decrement */ +#define RB_CNT_TST_ON BIT_18 /* Packet Counter Test On */ +#define RB_CNT_TST_OFF BIT_17 /* Packet Counter Test Off */ +#define RB_CNT_UP BIT_16 /* Packet Counter Increment */ + /* Bit 15: reserved */ +#define RB_WP_TST_ON BIT_14 /* Write Pointer Test On */ +#define RB_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ +#define RB_WP_UP BIT_12 /* Write Pointer Increment */ + /* Bit 11: reserved */ +#define RB_RP_TST_ON BIT_10 /* Read Pointer Test On */ +#define RB_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ +#define RB_RP_UP BIT_8 /* Read Pointer Increment */ + /* Receive and Transmit MAC FIFO Registers (GENESIS only) */ @@ -1372,7 +1818,7 @@ /* Bit 7: reserved */ #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */ #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */ -#define MFF_WP_INC BIT_4S /* Write Pointer Increm */ +#define MFF_WP_INC BIT_4S /* Write Pointer Increment */ /* Bit 3: reserved */ #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */ #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */ @@ -1391,12 +1837,16 @@ /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ + /* Bit 7.. 3: reserved */ +#define LED_START BIT_2S /* Start Counter */ +#define LED_STOP BIT_1S /* Stop Counter */ +#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED On */ + /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ /* Bit 7.. 3: reserved */ -#define LED_START BIT_2S /* Start Timer */ -#define LED_STOP BIT_1S /* Stop Timer */ -#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */ -#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */ +#define LNK_START BIT_2S /* Start Counter */ +#define LNK_STOP BIT_1S /* Stop Counter */ +#define LNK_CLR_IRQ BIT_0S /* Clear Link IRQ */ /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ @@ -1407,13 +1857,13 @@ #define LED_T_STEP BIT_0S /* LED Counter Step */ /* LNK_LED_REG 8 bit Link LED Register */ - /* Bit 7.. 6: reserved */ + /* Bit 7.. 6: reserved */ #define LED_BLK_ON BIT_5S /* Link LED Blinking On */ #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */ #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */ #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */ -#define LED_ON BIT_1S /* switch LED on */ -#define LED_OFF BIT_0S /* switch LED off */ +#define LED_ON BIT_1S /* Switch LED On */ +#define LED_OFF BIT_0S /* Switch LED Off */ /* Receive and Transmit GMAC FIFO Registers (YUKON only) */ @@ -1433,60 +1883,111 @@ /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ - /* Bits 31..15: reserved */ -#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ -#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ -#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ + /* Bit 31..28 reserved */ +#define RX_TRUNC_ON BIT_27 /* enable packet truncation */ +#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ +#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ +#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ + /* Bit 23..15 reserved */ +#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ +#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ +#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ /* Bit 11: reserved */ -#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ -#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ -#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ -#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ -#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ -#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ -#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ -#define GMF_OPER_ON BIT_3 /* Operational Mode On */ -#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ -#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ -#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ - -/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ - /* Bits 31..19: reserved */ -#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ -#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ -#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ - /* Bits 15..7: same as for RX_GMF_CTRL_T */ -#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ -#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ -#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ +#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ +#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ +#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ +#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ +#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ +#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ +#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ +#define GMF_OPER_ON BIT_3 /* Operational Mode On */ +#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ +#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ +#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ + +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ + /* Bits 31..26: reserved */ +#define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ +#define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ + /* Bits 23..19: reserved */ +#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ +#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ +#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ + /* Bits 15..8: same as for RX_GMF_CTRL_T */ + /* Bit 7: reserved */ +#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ +#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ +#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ /* Bits 3..0: same as for RX_GMF_CTRL_T */ #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) #define GMF_TX_CTRL_DEF GMF_OPER_ON +#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ - /* Bit 7.. 3: reserved */ -#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */ -#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */ -#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */ - + /* Bit 7.. 3: reserved */ +#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */ +#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */ +#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */ + +/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ + /* Bit 31.. 6: reserved */ +#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ +#define PC_POLL_RQ BIT_4 /* Poll Request Start */ +#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ +#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ +#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ +#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ + + +/* The bit definition of the following registers is still missing! */ +/* B28_Y2_SMB_CONFIG 32 bit ASF SMBus Config Register */ +/* B28_Y2_SMB_CSD_REG 32 bit ASF SMB Control/Status/Data */ +/* B28_Y2_ASF_IRQ_V_BASE 32 bit ASF IRQ Vector Base */ + +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ +/* This register is used by the host driver software */ + /* Bit 31:5 reserved */ +#define Y2_ASF_OS_PRES BIT_4 /* ASF operationg system present */ +#define Y2_ASF_UC_STATE (BIT_3|BIT_2) /* ASF uC State */ +#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ +#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ +#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ +#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ +#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ + +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ +/* This register is used by the ASF firmware */ + /* Bit 31:2 reserved */ +#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ +#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ + + +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ + /* Bit 7.. 5: reserved */ +#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ +#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ +#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ +#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ +#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ + /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ /* Bits 31.. 8: reserved */ -#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ -#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ -#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ -#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ -#define GMC_PAUSE_ON BIT_3 /* Pause On */ -#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ -#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ -#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ +#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ +#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ +#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ +#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ +#define GMC_PAUSE_ON BIT_3 /* Pause On */ +#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ +#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ +#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ /* Bits 31..29: reserved */ #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ -#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */ +#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ @@ -1540,14 +2041,14 @@ /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ -#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */ -#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */ -#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ -#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ -#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ -#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ +#define GM_IS_RX_CO_OV BIT_5S /* Receive Counter Overflow IRQ */ +#define GM_IS_TX_CO_OV BIT_4S /* Transmit Counter Overflow IRQ */ +#define GM_IS_TX_FF_UR BIT_3S /* Transmit FIFO Underrun */ +#define GM_IS_TX_COMPL BIT_2S /* Frame Transmission Complete */ +#define GM_IS_RX_FF_OR BIT_1S /* Receive FIFO Overrun */ +#define GM_IS_RX_COMPL BIT_0S /* Frame Reception Complete */ -#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \ +#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \ GM_IS_TX_FF_UR) /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ @@ -1579,15 +2080,19 @@ #define WOL_CTL_DEFAULT \ (WOL_CTL_DIS_PME_ON_LINK_CHG | \ - WOL_CTL_DIS_PME_ON_PATTERN | \ - WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ - WOL_CTL_DIS_LINK_CHG_UNIT | \ - WOL_CTL_DIS_PATTERN_UNIT | \ - WOL_CTL_DIS_MAGIC_PKT_UNIT) + WOL_CTL_DIS_PME_ON_PATTERN | \ + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ + WOL_CTL_DIS_LINK_CHG_UNIT | \ + WOL_CTL_DIS_PATTERN_UNIT | \ + WOL_CTL_DIS_MAGIC_PKT_UNIT) /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) +/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ +#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ +#define WOL_PATT_MATCH_PME_ALL 0x7f + #define SK_NUM_WOL_PATTERN 7 #define SK_PATTERN_PER_WORD 4 #define SK_BITMASK_PATTERN 7 @@ -1606,17 +2111,17 @@ SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */ SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */ SK_U32 TxStat; /* Transmit Frame Status Word */ -#ifndef SK_USE_REV_DESC +#ifndef SK_USE_REV_DESC SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ SK_U16 TxRes1; /* 16 bit reserved field */ SK_U16 TxTcpWp; /* TCP Checksum Write Position */ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ -#else /* SK_USE_REV_DESC */ +#else /* SK_USE_REV_DESC */ SK_U16 TxRes1; /* 16 bit reserved field */ SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ SK_U16 TxTcpWp; /* TCP Checksum Write Position */ -#endif /* SK_USE_REV_DESC */ +#endif /* SK_USE_REV_DESC */ SK_U32 TxRes2; /* 32 bit reserved field */ } SK_HWTXD; @@ -1628,29 +2133,260 @@ SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */ SK_U32 RxStat; /* Receive Frame Status Word */ SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */ -#ifndef SK_USE_REV_DESC - SK_U16 RxTcpSum1; /* TCP Checksum 1 */ - SK_U16 RxTcpSum2; /* TCP Checksum 2 */ +#ifndef SK_USE_REV_DESC + SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */ + SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ -#else /* SK_USE_REV_DESC */ - SK_U16 RxTcpSum2; /* TCP Checksum 2 */ - SK_U16 RxTcpSum1; /* TCP Checksum 1 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */ + SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ -#endif /* SK_USE_REV_DESC */ +#endif /* SK_USE_REV_DESC */ } SK_HWRXD; /* * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2) * should set the define SK_USE_REV_DESC. - * Structures are 'normaly' not endianess dependent. But in - * this case the SK_U16 fields are bound to bit positions inside the - * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord. + * Structures are 'normally' not endianess dependent. But in this case + * the SK_U16 fields are bound to bit positions inside the descriptor. + * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord. * The bit positions inside a DWord are of course endianess dependent and - * swaps if the DWord is swapped by the hardware. + * swap if the DWord is swapped by the hardware. */ +/* YUKON-2 descriptors ******************************************************/ + +typedef struct _TxChksum { +#ifndef SK_USE_REV_DESC + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ +#else /* SK_USE_REV_DESC */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ +#endif /* SK_USE_REV_DESC */ +} SK_HWTXCS; + +typedef struct _LargeSend { +#ifndef SK_USE_REV_DESC + SK_U16 Length; /* Large Send Segment Length */ + SK_U16 Reserved; /* reserved */ +#else /* SK_USE_REV_DESC */ + SK_U16 Reserved; /* reserved */ + SK_U16 Length; /* Large Send Segment Length */ +#endif /* SK_USE_REV_DESC */ +} SK_HWTXLS; + +typedef union u_HwTxBuf { + SK_U16 BufLen; /* Tx Buffer Length */ + SK_U16 VlanTag; /* VLAN Tag */ + SK_U16 InitCsum; /* Init. Checksum */ +} SK_HWTXBUF; + +/* Tx List Element structure */ +typedef struct s_HwLeTx { + union { + SK_U32 BufAddr; /* Tx LE Buffer Address high/low */ + SK_HWTXCS ChkSum; /* Tx LE TCP Checksum parameters */ + SK_HWTXLS LargeSend;/* Large Send length */ + } TxUn; +#ifndef SK_USE_REV_DESC + SK_HWTXBUF Send; + SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */ + SK_U8 Opcode; /* Tx LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U8 Opcode; /* Tx LE Opcode field */ + SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */ + SK_HWTXBUF Send; +#endif /* SK_USE_REV_DESC */ +} SK_HWLETX; + +typedef struct _RxChkSum{ +#ifndef SK_USE_REV_DESC + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ +#endif /* SK_USE_REV_DESC */ +} SK_HWRXCS; + +/* Rx List Element structure */ +typedef struct s_HwLeRx { + union { + SK_U32 BufAddr; /* Rx LE Buffer Address high/low */ + SK_HWRXCS ChkSum; /* Rx LE TCP Checksum parameters */ + } RxUn; +#ifndef SK_USE_REV_DESC + SK_U16 BufferLength; /* Rx LE Buffer Length field */ + SK_U8 ControlFlags; /* Rx LE Control field */ + SK_U8 Opcode; /* Rx LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U8 Opcode; /* Rx LE Opcode field */ + SK_U8 ControlFlags; /* Rx LE Control field */ + SK_U16 BufferLength; /* Rx LE Buffer Length field */ +#endif /* SK_USE_REV_DESC */ +} SK_HWLERX; + +typedef struct s_StRxTCPChkSum { +#ifndef SK_USE_REV_DESC + SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */ + SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */ + SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */ +#endif /* SK_USE_REV_DESC */ +} SK_HWSTCS; + +typedef struct s_StRxRssFlags { +#ifndef SK_USE_REV_DESC + SK_U8 FlagField; /* contains TCP and IP flags */ + SK_U8 reserved; /* reserved */ +#else /* SK_USE_REV_DESC */ + SK_U8 reserved; /* reserved */ + SK_U8 FlagField; /* contains TCP and IP flags */ +#endif /* SK_USE_REV_DESC */ +} SK_HWSTRSS; + +/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */ + /* bit 7..2 reserved */ +#define RSS_TCP_FLAG BIT_1S /* RSS value related to TCP area */ +#define RSS_IP_FLAG BIT_0S /* RSS value related to IP area */ +/* StRxRssValue is valid if at least RSS_IP_FLAG is set. */ +/* For protocol errors or other protocols an empty RSS LE is generated. */ + +typedef union u_HwStBuf { + SK_U16 BufLen; /* Rx Buffer Length */ + SK_U16 VlanTag; /* VLAN Tag */ + SK_U16 StTxStatHi; /* Tx Queue Status (high) */ + SK_HWSTRSS Rss; /* Flag Field for TCP and IP protocol */ +} SK_HWSTBUF; + +/* Status List Element structure */ +typedef struct s_HwLeSt { + union { + SK_U32 StRxStatWord; /* Rx Status Dword */ + SK_U32 StRxTimeStamp; /* Rx Timestamp */ + SK_HWSTCS StRxTCPCSum; /* Rx TCP Checksum */ + SK_U32 StTxStatLow; /* Tx Queue Status (low) */ + SK_U32 StRxRssValue; /* Rx RSS value */ + } StUn; +#ifndef SK_USE_REV_DESC + SK_HWSTBUF Stat; + SK_U8 Link; /* Status LE Link field */ + SK_U8 Opcode; /* Status LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U8 Opcode; /* Status LE Opcode field */ + SK_U8 Link; /* Status LE Link field */ + SK_HWSTBUF Stat; +#endif /* SK_USE_REV_DESC */ +} SK_HWLEST; + +/* Special Action List Element */ +typedef struct s_HwLeSa { +#ifndef SK_USE_REV_DESC + SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */ + SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */ + SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */ + SK_U8 Link; /* Special Action LE Link field */ + SK_U8 Opcode; /* Special Action LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */ + SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */ + SK_U8 Opcode; /* Special Action LE Opcode field */ + SK_U8 Link; /* Special Action LE Link field */ + SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */ +#endif /* SK_USE_REV_DESC */ +} SK_HWLESA; + +/* Common List Element union */ +typedef union u_HwLeTxRxSt { + /* transmit list element structure */ + SK_HWLETX Tx; + /* receive list element structure */ + SK_HWLERX Rx; + /* status list element structure */ + SK_HWLEST St; + /* special action list element structure */ + SK_HWLESA Sa; +} SK_HWLE; + +/* mask and shift value to get tx async queue status for port 1 */ +#define STLE_TXA1_MSKL 0x00000fff +#define STLE_TXA1_SHIFTL 0 + +/* mask and shift value to get tx sync queue status for port 1 */ +#define STLE_TXS1_MSKL 0x00fff000 +#define STLE_TXS1_SHIFTL 12 + +/* mask and shift value to get tx async queue status for port 2 */ +#define STLE_TXA2_MSKL 0xff000000 +#define STLE_TXA2_SHIFTL 24 +#define STLE_TXA2_MSKH 0x000f +/* this one shifts up */ +#define STLE_TXA2_SHIFTH 8 + +/* mask and shift value to get tx sync queue status for port 2 */ +#define STLE_TXS2_MSKL 0x00000000 +#define STLE_TXS2_SHIFTL 0 +#define STLE_TXS2_MSKH 0xfff0 +#define STLE_TXS2_SHIFTH 4 + +/* YUKON-2 bit values */ +#define HW_OWNER BIT_7 +#define SW_OWNER 0 + +#define PU_PUTIDX_VALID BIT_12 + +/* YUKON-2 Control flags */ +#define UDPTCP BIT_0S +#define CALSUM BIT_1S +#define WR_SUM BIT_2S +#define INIT_SUM BIT_3S +#define LOCK_SUM BIT_4S +#define INS_VLAN BIT_5S +#define FRC_STAT BIT_6S +#define EOP BIT_7S + +#define TX_LOCK BIT_8S +#define BUF_SEND BIT_9S +#define PACKET_SEND BIT_10S + +#define NO_WARNING BIT_14S +#define NO_UPDATE BIT_15S + +/* YUKON-2 Rx/Tx opcodes defines */ +#define OP_TCPWRITE 0x11 +#define OP_TCPSTART 0x12 +#define OP_TCPINIT 0x14 +#define OP_TCPLCK 0x18 +#define OP_TCPCHKSUM OP_TCPSTART +#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) +#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) +#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) +#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) +#define OP_ADDR64 0x21 +#define OP_VLAN 0x22 +#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) +#define OP_LRGLEN 0x24 +#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) +#define OP_BUFFER 0x40 +#define OP_PACKET 0x41 +#define OP_LARGESEND 0x43 + +/* YUKON-2 STATUS opcodes defines */ +#define OP_RXSTAT 0x60 +#define OP_RXTIMESTAMP 0x61 +#define OP_RXVLAN 0x62 +#define OP_RXCHKS 0x64 +#define OP_RXCHKSVLAN ( OP_RXCHKS | OP_RXVLAN ) +#define OP_RXTIMEVLAN ( OP_RXTIMESTAMP | OP_RXVLAN ) +#define OP_RSS_HASH 0x65 +#define OP_TXINDEXLE 0x68 + +/* YUKON-2 SPECIAL opcodes defines */ +#define OP_PUTIDX 0x70 /* Descriptor Bit Definition */ /* TxCtrl Transmit Buffer Control Field */ @@ -1685,6 +2421,10 @@ /* macros ********************************************************************/ +/* Macro fro accessing the key registers */ +#define RSS_KEY_ADDR(Port, KeyIndex) \ + ((B4_RSS_KEY | ( ((Port)!=0) ? 0x80 : 0))+(KeyIndex)) + /* Receive and Transmit Queues */ #define Q_R1 0x0000 /* Receive Queue 1 */ #define Q_R2 0x0080 /* Receive Queue 2 */ @@ -1693,6 +2433,10 @@ #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ +#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ +#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ +#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ +#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ /* * Macro Q_ADDR() * @@ -1704,11 +2448,27 @@ * Offs Queue register offset. * Values: Q_D, Q_DA_L ... Q_T2, Q_T3 * - * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal) + * usage SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal) */ #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) /* + * Macro Y2_PREF_Q_ADDR() + * + * Use this macro to access the Prefetch Units of the receive and + * transmit queues of Yukon-2. + * + * para: + * Queue Queue to access. + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2, + * Offs Queue register offset. + * Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG + * + * usage SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal) + */ +#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) + +/* * Macro RB_ADDR() * * Use this macro to access the RAM Buffer Registers. @@ -1719,14 +2479,14 @@ * Offs Queue register offset. * Values: RB_START, RB_END ... RB_LEV, RB_CTRL * - * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal) + * usage SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal) */ #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) /* MAC Related Registers */ -#define MAC_1 0 /* belongs to the port near the slot */ -#define MAC_2 1 /* belongs to the port far away from the slot */ +#define MAC_1 0 /* 1st port */ +#define MAC_2 1 /* 2nd port */ /* * Macro MR_ADDR() @@ -1740,18 +2500,17 @@ * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG, * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST * - * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal) + * usage SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal) */ #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) -#ifdef SK_LITTLE_ENDIAN +#ifdef SK_LITTLE_ENDIAN #define XM_WORD_LO 0 #define XM_WORD_HI 1 -#else /* !SK_LITTLE_ENDIAN */ +#else /* !SK_LITTLE_ENDIAN */ #define XM_WORD_LO 1 #define XM_WORD_HI 0 -#endif /* !SK_LITTLE_ENDIAN */ - +#endif /* !SK_LITTLE_ENDIAN */ /* * macros to access the XMAC (GENESIS only) @@ -2071,12 +2830,14 @@ * Use this macro to access PCI config register from the I/O space. * * para: + * pAC Pointer to adapter context * Addr PCI configuration register to access. * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG, * - * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal); + * usage SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal); */ -#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */ +#define PCI_C(p, Addr) \ + (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr)) /* * Macro SK_HW_ADDR(Base, Addr) @@ -2088,7 +2849,7 @@ * Addr Address offset * * usage: May be used in SK_INxx and SK_OUTxx macros - * #define SK_IN8(pAC, Addr, pVal) ...\ + * #define SK_IN8(IoC, Addr, pVal) ...\ * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr))) */ #ifdef SK_MEM_MAPPED_IO @@ -2113,6 +2874,21 @@ #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \ SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode); +#define SK_SET_GPIO(IoC, Bit) { \ + SK_U32 DWord; \ + SK_IN32(IoC, B2_GP_IO, &DWord); \ + DWord |= ((GP_DIR_0 << (Bit)) | (GP_IO_0 << (Bit)));\ + SK_OUT32(IoC, B2_GP_IO, DWord); \ +} + +#define SK_CLR_GPIO(IoC, Bit) { \ + SK_U32 DWord; \ + SK_IN32(IoC, B2_GP_IO, &DWord); \ + DWord &= ~(GP_IO_0 << (Bit)); \ + SK_OUT32(IoC, B2_GP_IO, DWord); \ +} + +#define SK_GE_PCI_FIFO_SIZE 1600 /* PCI FIFO Size */ /* typedefs *******************************************************************/ @@ -2124,3 +2900,4 @@ #endif /* __cplusplus */ #endif /* __INC_SKGEHW_H */ + diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h --- linux/drivers/net/sk98lin/h/skgehwt.h 2004-08-14 12:55:19.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgehwt.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skhwt.h * Project: Gigabit Ethernet Adapters, Event Scheduler Module - * Version: $Revision: 1.7 $ - * Date: $Date: 2003/09/16 12:55:08 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:09 $ * Purpose: Defines for the hardware timer functions * ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skgei2c.h linux-new/drivers/net/sk98lin/h/skgei2c.h --- linux/drivers/net/sk98lin/h/skgei2c.h 2004-08-14 12:55:48.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,210 +0,0 @@ -/****************************************************************************** - * - * Name: skgei2c.h - * Project: Gigabit Ethernet Adapters, TWSI-Module - * Version: $Revision: 1.25 $ - * Date: $Date: 2003/10/20 09:06:05 $ - * Purpose: Special defines for TWSI - * - ******************************************************************************/ - -/****************************************************************************** - * - * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/* - * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling - */ - -#ifndef _INC_SKGEI2C_H_ -#define _INC_SKGEI2C_H_ - -/* - * Macros to access the B2_I2C_CTRL - */ -#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \ - SK_OUT32(IoC, B2_I2C_CTRL,\ - (flag ? 0x80000000UL : 0x0L) | \ - (((SK_U32)reg << 16) & I2C_ADDR) | \ - (((SK_U32)dev << 9) & I2C_DEV_SEL) | \ - (dev_size & I2C_DEV_SIZE) | \ - ((burst << 4) & I2C_BURST_LEN)) - -#define SK_I2C_STOP(IoC) { \ - SK_U32 I2cCtrl; \ - SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \ - SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \ -} - -#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl) - -/* - * Macros to access the TWSI SW Registers - */ -#define SK_I2C_SET_BIT(IoC, SetBits) { \ - SK_U8 OrgBits; \ - SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ - SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \ -} - -#define SK_I2C_CLR_BIT(IoC, ClrBits) { \ - SK_U8 OrgBits; \ - SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ - SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \ -} - -#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw) - -/* - * define the possible sensor states - */ -#define SK_SEN_IDLE 0 /* Idle: sensor not read */ -#define SK_SEN_VALUE 1 /* Value Read cycle */ -#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */ - -/* - * Conversion factor to convert read Voltage sensor to milli Volt - * Conversion factor to convert read Temperature sensor to 10th degree Celsius - */ -#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */ -#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */ -#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */ - -/* - * formula: counter = (22500*60)/(rpm * divisor * pulses/2) - * assuming: 6500rpm, 4 pulses, divisor 1 - */ -#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2)) - -/* - * Define sensor management data - * Maximum is reached on Genesis copper dual port and Yukon-64 - * Board specific maximum is in pAC->I2c.MaxSens - */ -#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */ -#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */ - -/* - * To watch the state machine (SM) use the timer in two ways - * instead of one as hitherto - */ -#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */ -#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ - -/* - * Defines for the individual thresholds - */ - -/* Temperature sensor */ -#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */ -#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */ -#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */ -#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */ - -/* VCC which should be 5 V */ -#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ -#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */ -#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */ -#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */ - -/* - * VIO may be 5 V or 3.3 V. Initialization takes two parts: - * 1. Initialize lowest lower limit and highest higher limit. - * 2. After the first value is read correct the upper or the lower limit to - * the appropriate C constant. - * - * Warning limits are +-5% of the exepected voltage. - * Error limits are +-10% of the expected voltage. - */ - -/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */ - -#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */ -#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */ - /* 5000 mVolt */ -#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */ -#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */ - -#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */ - -/* correction values for the second pass */ -#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */ -#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */ - /* 3300 mVolt */ -#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */ -#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */ - -/* - * VDD voltage - */ -#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */ -#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */ -#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */ -#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */ - -/* - * PHY PLL 3V3 voltage - */ -#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */ -#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */ -#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */ -#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */ - -/* - * VAUX (YUKON only) - */ -#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */ -#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */ -#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */ -#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */ -#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */ -#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */ - -/* - * PHY 2V5 voltage - */ -#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */ -#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */ -#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */ -#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */ - -/* - * ASIC Core 1V5 voltage (YUKON only) - */ -#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */ -#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */ -#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */ -#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */ - -/* - * FAN 1 speed - */ -/* assuming: 6500rpm +-15%, 4 pulses, - * warning at: 80 % - * error at: 70 % - * no upper limit - */ -#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */ -#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */ -#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ -#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */ - -/* - * Some Voltages need dynamic thresholds - */ -#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */ -#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */ -#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */ - -extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); -#endif /* n_INC_SKGEI2C_H */ diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h --- linux/drivers/net/sk98lin/h/skgeinit.h 2004-08-14 12:55:48.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgeinit.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skgeinit.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.83 $ - * Date: $Date: 2003/09/16 14:07:37 $ + * Version: $Revision: 2.30 $ + * Date: $Date: 2004/08/13 09:12:18 $ * Purpose: Structures and prototypes for the GE Init Module * ******************************************************************************/ @@ -11,13 +11,12 @@ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -60,14 +59,17 @@ #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */ #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */ -#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */ +#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz (Genesis) */ +#define SK_DPOLL_DEF_Y2 0x0000124fUL /* 75 us (Yukon-2) */ #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */ - /* 215 ms at 78.12 MHz */ + /* 215 ms at 78.12 MHz (Yukon) */ #define SK_FACT_62 100 /* is given in percent */ #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */ +#define SK_FACT_100 161 /* on YUKON-FE: 100 MHz */ +#define SK_FACT_125 202 /* on YUKON-EC: 125 MHz */ /* Timeout values */ #define SK_MAC_TO_53 72 /* MAC arbiter timeout */ @@ -83,10 +85,16 @@ #define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ #ifndef SK_BMU_RX_WM -#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ +#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ #endif + #ifndef SK_BMU_TX_WM -#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ +#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ +#endif + +/* performance sensitive drivers should set this define to 0x80 */ +#ifndef SK_BMU_RX_WM_PEX +#define SK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ #endif /* XMAC II Rx High Watermark */ @@ -104,31 +112,25 @@ #define SK_JUMBO_LINK 3 /* driver uses jumbo frames */ /* Minimum RAM Buffer Rx Queue Size */ -#define SK_MIN_RXQ_SIZE 16 /* 16 kB */ +#define SK_MIN_RXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */ /* Minimum RAM Buffer Tx Queue Size */ -#define SK_MIN_TXQ_SIZE 16 /* 16 kB */ +#define SK_MIN_TXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */ -/* Queue Size units */ -#define QZ_UNITS 0x7 +/* Queue Size units (Genesis/Yukon) */ +#define QZ_UNITS 7 #define QZ_STEP 8 +/* Queue Size units (Yukon-2) */ +#define QZ_STEP_Y2 1 + /* Percentage of queue size from whole memory */ /* 80 % for receive */ -#define RAM_QUOTA_RX 80L +#define RAM_QUOTA_RX 80 /* 0% for sync transfer */ -#define RAM_QUOTA_SYNC 0L +#define RAM_QUOTA_SYNC 0 /* the rest (20%) is taken for async transfer */ -/* Get the rounded queue size in Bytes in 8k steps */ -#define ROUND_QUEUE_SIZE(SizeInBytes) \ - ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \ - ~(QZ_STEP-1)) - -/* Get the rounded queue size in KBytes in 8k steps */ -#define ROUND_QUEUE_SIZE_KB(Kilobytes) \ - ROUND_QUEUE_SIZE((Kilobytes) * 1024L) - /* Types of RAM Buffer Queues */ #define SK_RX_SRAM_Q 1 /* small receive queue */ #define SK_RX_BRAM_Q 2 /* big receive queue */ @@ -266,10 +268,15 @@ /* PHY power down modes */ #define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */ -#define PHY_PM_DEEP_SLEEP 1 /* coma mode --> minimal power */ +#define PHY_PM_DEEP_SLEEP 1 /* Coma mode --> minimal power */ #define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */ -#define PHY_PM_ENERGY_DETECT 3 /* energy detect */ -#define PHY_PM_ENERGY_DETECT_PLUS 4 /* energy detect plus */ +#define PHY_PM_ENERGY_DETECT 3 /* Energy detect */ +#define PHY_PM_ENERGY_DETECT_PLUS 4 /* Energy detect plus */ + +/* PCI Bus Types */ +#define SK_PCI_BUS 0x0001 /* normal PCI bus */ +#define SK_PCIX_BUS 0x0002 /* PCI-X bus */ +#define SK_PEX_BUS 0x0004 /* PCI-Express bus */ /* Default receive frame limit for Workaround of XMAC Errata */ #define SK_DEF_RX_WA_LIM SK_CONSTU64(100) @@ -278,6 +285,7 @@ #define SK_ACT_LED_BLINK (1<<0) /* Active LED blinking */ #define SK_DUP_LED_NORMAL (1<<1) /* Duplex LED normal */ #define SK_LED_LINK100_ON (1<<2) /* Link 100M LED on */ +#define SK_DUAL_LED_ACT_LNK (1<<3) /* Dual LED ACT/LNK configuration */ /* Link Partner Status */ #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */ @@ -290,18 +298,160 @@ /* Max. Auto-neg. timeouts before link detection in sense mode is reset */ #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */ + +/****************************************************************************** + * + * HW_FEATURE() macro + */ + +/* DWORD 0: Features */ +#define HWF_SYNC_TX_SUP 0x00800000UL /* synch tx queue available */ +#define HWF_SINGLE_PORT_DEVICE 0x00400000UL /* device has only one LAN IF */ +#define HWF_JUMBO_FRAMES_SUP 0x00200000UL /* Jumbo frames supported */ +#define HWF_TX_TCP_CSUM_SUP 0x00100000UL /* TCP tx checksum supported */ +#define HWF_TX_UDP_CSUM_SUP 0x00080000UL /* UDP tx checksum supported */ +#define HWF_RX_CSUM_SUP 0x00040000UL /* RX checksum supported */ +#define HWF_TCP_SEGM_SUP 0x00020000UL /* TCP segmentation supported */ +#define HWF_RSS_HASH_SUP 0x00010000UL /* RSS Hash supported */ +#define HWF_PORT_VLAN_SUP 0x00008000UL /* VLAN can be config per port*/ +#define HWF_ROLE_PARAM_SUP 0x00004000UL /* Role parameter supported */ +#define HWF_LOW_PMODE_SUP 0x00002000UL /* Low Power Mode supported */ +#define HWF_ENERGIE_DEMO_SUP 0x00001000UL /* Energie detect mode supp. */ +#define HWF_SPEED1000_SUP 0x00000800UL /* Line Speed 1000 supported */ +#define HWF_SPEED100_SUP 0x00000400UL /* Line Speed 100 supported */ +#define HWF_SPEED10_SUP 0x00000200UL /* Line Speed 10 supported */ +#define HWF_AUTONEGSENSE_SUP 0x00000100UL /* Autoneg Sense supported */ +#define HWF_PHY_LOOPB_MD_SUP 0x00000080UL /* PHY loopback mode supp. */ +#define HWF_ASF_SUP 0x00000040UL /* ASF support possible */ +#define HWF_QS_STEPS_1kB 0x00000020UL /* The rx/tx queues can be */ + /* configured in units of 1 kB*/ +#define HWF_OWN_RAM_PER_PORT 0x00000010UL /* Each port has a separate */ + /* RAM buffer */ +#define HWF_MIN_LED_IF 0x00000008UL /* Minimal LED interface */ + /* (e.g. for Yukon-EC) */ +#define HWF_LIST_ELEMENTS_USED 0x00000004UL /* HW uses list elements */ + /* (otherwise desc. are used) */ +#define HWF_GMAC_INSIDE 0x00000002UL /* device contains GMAC */ +#define HWF_TWSI_PRESENT 0x00000001UL /* TWSI sensor bus present */ + +/*-RMV- DWORD 1: Deviations */ +#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */ +#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst)*/ +#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */ +#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */ + /*-RMV- compl&Stat BMU deadl) */ +#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */ +#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */ +#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg over wr)*/ +#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */ + /*-RMV- with odd offset) */ +#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/ +#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/ + /*-RMV- for Yu-L Rev. A0 only */ +#define HWF_WA_COMA_MODE 0x10000001UL /*-RMV- Coma Mode WA req */ + +/* DWORD 2: still unused */ +/* DWORD 3: still unused */ + + +/* + * HW_FEATURE() - returns whether the feature is serviced or not + */ +#define HW_FEATURE(pAC, ReqFeature) \ + (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\ + ((ReqFeature) & 0x0fffffffUL)) != 0) + +#define HW_FEAT_LIST 0 +#define HW_DEV_LIST 1 + +#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) { \ + if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) { \ + (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue); \ + (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue); \ + } \ +} + +/* driver access macros for GIni structure ***********************************/ + +#define CHIP_ID_YUKON_2(pAC) ((pAC)->GIni.GIYukon2) +#define HW_SYNC_TX_SUPPORTED(pAC) \ + ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC && \ + (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE) + +#define HW_MS_TO_TICKS(pAC, MsTime) \ + ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact) + +#if 0 +/* still under construction */ +#define HW_IS_SINGLE_PORT(pAC) ((pAC)->GIni.GIMacsFound == 1) +#define HW_NUMBER_OF_PORTS(pAC) ((pAC)->GIni.GIMacsFound) + +#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \ + ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0)) + +#define HW_DEFAULT_LINESPEED(pAC) \ + ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \ + SK_LSPEED_AUTO : SK_LSPEED_1000MBPS) + +#define HW_ROLE_PARAM_SUPPORTED(pAC) ((pAC)->GIni.GICopperType) + +#define HW_SPEED1000_SUPPORTED(pAC, Port) \ + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) + +#define HW_SPEED100_SUPPORTED(pAC, Port) \ + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) + +#define HW_SPEED10_SUPPORTED(pAC, Port) \ + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) + +#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC) + +#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \ + (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq) + +#define HW_IS_LINK_UP(pAC, Port) ((pAC)->GIni.GP[Port].PHWLinkUp) +#define HW_LINK_SPEED_USED(pAC, Port) ((pAC)->GIni.GP[Port].PLinkSpeedUsed) +#define HW_RAM_SIZE(pAC) ((pAC)->GIni.GIRamSize) + +#define HW_ENA_JUMBO_FRAME_SUPPORT(pAC) (pAC)->GIni.GIPortUsage = SK_JUMBO_LINK +#define HW_DIS_JUMBO_FRAME_SUPPORT(pAC) (pAC)->GIni.GIPortUsage = ???? +#define HW_PHY_LP_MODE_SUPPORTED(pAC) (pAC0->??? +#define HW_ASF_ACTIVE(pAC) ??? +#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)... + +/* macro to check whether tx csum is supported */ +#define HW_TX_CSUM_SUPPORTED(pAC) ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS) + +BMU_UDP_CHECK : BMU_TCP_CHECK; + +/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */ +#endif /* 0 */ + + /* structures *****************************************************************/ /* + * HW Feature structure + */ +typedef struct s_HwFeatures { + SK_U32 Features[4]; /* Feature list */ + SK_U32 OffMask[4]; /* Off Mask */ + SK_U32 OnMask[4]; /* On Mask */ +} SK_HW_FEATURES; + +/* * MAC specific functions */ typedef struct s_GeMacFunc { - int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); - int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, - SK_U16 StatAddr, SK_U32 SK_FAR *pVal); - int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); - int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, - SK_U16 IStatus, SK_U64 SK_FAR *pVal); + int (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int); + int (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *); + int (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int); + int (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *); + void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32); +#ifdef SK_DIAG + int (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *); + int (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16); +#endif /* SK_DIAG */ } SK_GEMACFUNC; /* @@ -311,7 +461,7 @@ #ifndef SK_DIAG SK_TIMER PWaTimer; /* Workaround Timer */ SK_TIMER HalfDupChkTimer; -#endif /* SK_DIAG */ +#endif /* !SK_DIAG */ SK_U32 PPrevShorts; /* Previous Short Counter checking */ SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */ SK_U64 PPrevRx; /* Previous RxOk Counter checking */ @@ -367,6 +517,8 @@ int PMacJamLen; /* MAC Jam length */ int PMacJamIpgVal; /* MAC Jam IPG */ int PMacJamIpgData; /* MAC IPG Jam to Data */ + int PMacBackOffLim; /* MAC Back-off Limit */ + int PMacDataBlind; /* MAC Data Blinder */ int PMacIpgData; /* MAC Data IPG */ SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */ } SK_GEPORT; @@ -379,18 +531,24 @@ int GIChipId; /* Chip Identification Number */ int GIChipRev; /* Chip Revision Number */ SK_U8 GIPciHwRev; /* PCI HW Revision Number */ + SK_U8 GIPciBus; /* PCI Bus Type (PCI / PCIX / PEX)*/ SK_BOOL GIGenesis; /* Genesis adapter ? */ - SK_BOOL GIYukon; /* YUKON-A1/Bx chip */ + SK_BOOL GIYukon; /* YUKON family (1 and 2) */ SK_BOOL GIYukonLite; /* YUKON-Lite chip */ + SK_BOOL GIYukon2; /* YUKON-2 chip (-XL, -EC or -FE) */ + SK_U8 GIConTyp; /* Connector Type */ + SK_U8 GIPmdTyp; /* PMD Type */ SK_BOOL GICopperType; /* Copper Type adapter ? */ SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */ SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */ SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */ SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */ + SK_BOOL GIAsfEnabled; /* ASF subsystem enabled */ SK_U16 GILedBlinkCtrl; /* LED Blink Control */ int GIMacsFound; /* Number of MACs found on this adapter */ int GIMacType; /* MAC Type used on this adapter */ - int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */ + int GIChipCap; /* Adapter's Capabilities */ + int GIHstClkFact; /* Host Clock Factor (HstClk / 62.5 * 100) */ int GIPortUsage; /* Driver Port Usage */ int GILevel; /* Initialization Level completed */ int GIRamSize; /* The RAM size of the adapter in kB */ @@ -398,8 +556,10 @@ SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */ SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */ SK_U32 GIValIrqMask; /* Value for Interrupt Mask */ + SK_U32 GIValHwIrqMask; /* Value for Interrupt Mask */ SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */ SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */ + SK_HW_FEATURES HwF; /* HW Features struct */ SK_GEMACFUNC GIFunc; /* MAC depedent functions */ } SK_GEINIT; @@ -464,6 +624,24 @@ /* * public functions in skgeinit.c */ +extern void SkGePortVlan( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkGeRxRss( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkGeRxCsum( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + extern void SkGePollRxD( SK_AC *pAC, SK_IOC IoC, @@ -624,28 +802,28 @@ int Port, SK_BOOL Enable); -extern void SkXmPhyRead( +extern int SkXmPhyRead( SK_AC *pAC, SK_IOC IoC, int Port, int Addr, SK_U16 SK_FAR *pVal); -extern void SkXmPhyWrite( +extern int SkXmPhyWrite( SK_AC *pAC, SK_IOC IoC, int Port, int Addr, SK_U16 Val); -extern void SkGmPhyRead( +extern int SkGmPhyRead( SK_AC *pAC, SK_IOC IoC, int Port, int Addr, SK_U16 SK_FAR *pVal); -extern void SkGmPhyWrite( +extern int SkGmPhyWrite( SK_AC *pAC, SK_IOC IoC, int Port, @@ -729,6 +907,7 @@ int Port, SK_BOOL StartTest); +#ifdef SK_PHY_LP_MODE extern int SkGmEnterLowPowerMode( SK_AC *pAC, SK_IOC IoC, @@ -739,6 +918,7 @@ SK_AC *pAC, SK_IOC IoC, int Port); +#endif /* SK_PHY_LP_MODE */ #ifdef SK_DIAG extern void SkGePhyRead( @@ -794,6 +974,9 @@ extern void SkGeXmitLED(); extern void SkGeInitRamIface(); extern int SkGeInitAssignRamToQueues(); +extern void SkGePortVlan(); +extern void SkGeRxCsum(); +extern void SkGeRxRss(); /* * public functions in skxmac2.c @@ -814,11 +997,11 @@ extern void SkMacAutoNegLipaPhy(); extern void SkMacSetRxTxEn(); extern void SkXmInitMac(); -extern void SkXmPhyRead(); -extern void SkXmPhyWrite(); +extern int SkXmPhyRead(); +extern int SkXmPhyWrite(); extern void SkGmInitMac(); -extern void SkGmPhyRead(); -extern void SkGmPhyWrite(); +extern int SkGmPhyRead(); +extern int SkGmPhyWrite(); extern void SkXmClrExactAddr(); extern void SkXmInitDupMd(); extern void SkXmInitPauseMd(); @@ -832,8 +1015,10 @@ extern int SkXmOverflowStatus(); extern int SkGmOverflowStatus(); extern int SkGmCableDiagStatus(); +#ifdef SK_PHY_LP_MODE extern int SkGmEnterLowPowerMode(); extern int SkGmLeaveLowPowerMode(); +#endif /* SK_PHY_LP_MODE */ #ifdef SK_DIAG extern void SkGePhyRead(); @@ -844,10 +1029,11 @@ extern void SkXmSendCont(); #endif /* SK_DIAG */ -#endif /* SK_KR_PROTO */ +#endif /* SK_KR_PROTO */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __INC_SKGEINIT_H_ */ + diff -ruN linux/drivers/net/sk98lin/h/skgepnm2.h linux-new/drivers/net/sk98lin/h/skgepnm2.h --- linux/drivers/net/sk98lin/h/skgepnm2.h 2004-08-14 12:55:35.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgepnm2.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skgepnm2.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.36 $ - * Date: $Date: 2003/05/23 12:45:13 $ + * Version: $Revision: 2.3 $ + * Date: $Date: 2004/03/19 16:19:59 $ * Purpose: Defines for Private Network Management Interface * ****************************************************************************/ @@ -70,9 +70,9 @@ /* * VCT internal status values */ -#define SK_PNMI_VCT_PENDING 32 -#define SK_PNMI_VCT_TEST_DONE 64 -#define SK_PNMI_VCT_LINK 128 +#define SK_PNMI_VCT_PENDING 0x20 +#define SK_PNMI_VCT_TEST_DONE 0x40 +#define SK_PNMI_VCT_LINK 0x80 /* * Internal table definitions @@ -323,7 +323,7 @@ vSt, \ pAC->Pnmi.MacUpdatedFlag, \ pAC->Pnmi.RlmtUpdatedFlag, \ - pAC->Pnmi.SirqUpdatedFlag))}} + pAC->Pnmi.SirqUpdatedFlag));}} #else /* !DEBUG */ diff -ruN linux/drivers/net/sk98lin/h/skgepnmi.h linux-new/drivers/net/sk98lin/h/skgepnmi.h --- linux/drivers/net/sk98lin/h/skgepnmi.h 2004-08-14 12:54:49.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgepnmi.h 2004-08-26 10:27:59.000000000 +0200 @@ -1,9 +1,9 @@ /***************************************************************************** * * Name: skgepnmi.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.62 $ - * Date: $Date: 2003/08/15 12:31:52 $ + * Project: Gigabit Ethernet Adapters, PNMI-Module + * Version: $Revision: 2.8 $ + * Date: $Date: 2004/06/14 06:55:26 $ * Purpose: Defines for Private Network Management Interface * ****************************************************************************/ @@ -31,7 +31,7 @@ #include "h/sktypes.h" #include "h/skerror.h" #include "h/sktimer.h" -#include "h/ski2c.h" +#include "h/sktwsi.h" #include "h/skaddr.h" #include "h/skrlmt.h" #include "h/skvpd.h" @@ -41,7 +41,6 @@ */ #define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */ - /* * Event definitions */ @@ -54,16 +53,13 @@ #define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */ #define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */ #define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */ - #define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */ #define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */ #define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */ #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */ #define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */ -#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets - 1 = single net; 2 = dual net */ -#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ - +#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* Number of nets (1 or 2). */ +#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ /* * Return values @@ -78,7 +74,6 @@ #define SK_PNMI_ERR_UNKNOWN_NET 7 #define SK_PNMI_ERR_NOT_SUPPORTED 10 - /* * Return values of driver reset function SK_DRIVER_RESET() and * driver event function SK_DRIVER_EVENT() @@ -86,19 +81,17 @@ #define SK_PNMI_ERR_OK 0 #define SK_PNMI_ERR_FAIL 1 - /* * Return values of driver test function SK_DRIVER_SELFTEST() */ #define SK_PNMI_TST_UNKNOWN (1 << 0) -#define SK_PNMI_TST_TRANCEIVER (1 << 1) +#define SK_PNMI_TST_TRANCEIVER (1 << 1) #define SK_PNMI_TST_ASIC (1 << 2) #define SK_PNMI_TST_SENSOR (1 << 3) -#define SK_PNMI_TST_POWERMGMT (1 << 4) +#define SK_PNMI_TST_POWERMGMT (1 << 4) #define SK_PNMI_TST_PCI (1 << 5) #define SK_PNMI_TST_MAC (1 << 6) - /* * RLMT specific definitions */ @@ -352,6 +345,7 @@ #define OID_SKGE_VCT_GET 0xFF020200 #define OID_SKGE_VCT_SET 0xFF020201 #define OID_SKGE_VCT_STATUS 0xFF020202 +#define OID_SKGE_VCT_CAPABILITIES 0xFF020203 #ifdef SK_DIAG_SUPPORT /* Defines for driver DIAG mode. */ @@ -367,22 +361,66 @@ #define OID_SKGE_PHY_TYPE 0xFF020215 #define OID_SKGE_PHY_LP_MODE 0xFF020216 +/* + * Added for new DualNet IM driver V2 + * these OIDs should later be in pnmi.h + */ +#define OID_SKGE_MAC_COUNT 0xFF020217 +#define OID_SKGE_DUALNET_MODE 0xFF020218 +#define OID_SKGE_SET_TAGHEADER 0xFF020219 + +#ifdef SK_ASF +/* Defines for ASF */ +#define OID_SKGE_ASF 0xFF02021a +#define OID_SKGE_ASF_STORE_CONFIG 0xFF02021b +#define OID_SKGE_ASF_ENA 0xFF02021c +#define OID_SKGE_ASF_RETRANS 0xFF02021d +#define OID_SKGE_ASF_RETRANS_INT 0xFF02021e +#define OID_SKGE_ASF_HB_ENA 0xFF02021f +#define OID_SKGE_ASF_HB_INT 0xFF020220 +#define OID_SKGE_ASF_WD_ENA 0xFF020221 +#define OID_SKGE_ASF_WD_TIME 0xFF020222 +#define OID_SKGE_ASF_IP_SOURCE 0xFF020223 +#define OID_SKGE_ASF_MAC_SOURCE 0xFF020224 +#define OID_SKGE_ASF_IP_DEST 0xFF020225 +#define OID_SKGE_ASF_MAC_DEST 0xFF020226 +#define OID_SKGE_ASF_COMMUNITY_NAME 0xFF020227 +#define OID_SKGE_ASF_RSP_ENA 0xFF020228 +#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229 +#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a +#define OID_SKGE_ASF_RETRANS_INT_MIN 0xFF02022b +#define OID_SKGE_ASF_RETRANS_INT_MAX 0xFF02022c +#define OID_SKGE_ASF_HB_INT_MIN 0xFF02022d +#define OID_SKGE_ASF_HB_INT_MAX 0xFF02022e +#define OID_SKGE_ASF_WD_TIME_MIN 0xFF02022f +#define OID_SKGE_ASF_WD_TIME_MAX 0xFF020230 +#define OID_SKGE_ASF_HB_CAP 0xFF020231 +#define OID_SKGE_ASF_WD_TIMER_RES 0xFF020232 +#define OID_SKGE_ASF_GUID 0xFF020233 +#define OID_SKGE_ASF_KEY_OP 0xFF020234 +#define OID_SKGE_ASF_KEY_ADM 0xFF020235 +#define OID_SKGE_ASF_KEY_GEN 0xFF020236 +#define OID_SKGE_ASF_CAP 0xFF020237 +#define OID_SKGE_ASF_PAR_1 0xFF020238 +#define OID_SKGE_ASF_OVERALL_OID 0xFF020239 +#endif /* SK_ASF */ + /* VCT struct to store a backup copy of VCT data after a port reset. */ typedef struct s_PnmiVct { SK_U8 VctStatus; - SK_U8 PCableLen; - SK_U32 PMdiPairLen[4]; - SK_U8 PMdiPairSts[4]; + SK_U8 CableLen; + SK_U32 MdiPairLen[4]; + SK_U8 MdiPairSts[4]; } SK_PNMI_VCT; /* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */ -#define SK_PNMI_VCT_NONE 0 -#define SK_PNMI_VCT_OLD_VCT_DATA 1 -#define SK_PNMI_VCT_NEW_VCT_DATA 2 -#define SK_PNMI_VCT_OLD_DSP_DATA 4 -#define SK_PNMI_VCT_NEW_DSP_DATA 8 -#define SK_PNMI_VCT_RUNNING 16 +#define SK_PNMI_VCT_NONE 0x00 +#define SK_PNMI_VCT_OLD_VCT_DATA 0x01 +#define SK_PNMI_VCT_NEW_VCT_DATA 0x02 +#define SK_PNMI_VCT_OLD_DSP_DATA 0x04 +#define SK_PNMI_VCT_NEW_DSP_DATA 0x08 +#define SK_PNMI_VCT_RUNNING 0x10 /* VCT cable test status. */ @@ -390,7 +428,12 @@ #define SK_PNMI_VCT_SHORT_CABLE 1 #define SK_PNMI_VCT_OPEN_CABLE 2 #define SK_PNMI_VCT_TEST_FAIL 3 -#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 +#define SK_PNMI_VCT_NOT_PRESENT 5 + +/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */ +#define SK_PNMI_VCT_SUPPORTED 1 +#define SK_PNMI_VCT_NOT_SUPPORTED 0 #define OID_SKGE_TRAP_SEN_WAR_LOW 500 #define OID_SKGE_TRAP_SEN_WAR_UPP 501 @@ -419,7 +462,6 @@ #define SK_SET_FULL_MIB 5 #define SK_PRESET_FULL_MIB 6 - /* * Define error numbers and messages for syslog */ @@ -452,7 +494,7 @@ #define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14) #define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys" #define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15) -#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small" +#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys too small" #define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16) #define SK_PNMI_ERR016MSG "Vpd: Key string too long" #define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17) @@ -494,9 +536,9 @@ #define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36) #define SK_PNMI_ERR036MSG "" #define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37) -#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0" +#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0" #define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38) -#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0" +#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0" #define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39) #define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID" #define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40) @@ -514,9 +556,9 @@ #define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46) #define SK_PNMI_ERR046MSG "Monitor: Unknown OID" #define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47) -#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0" +#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returned not 0" #define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48) -#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0" +#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returned not 0" #define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49) #define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!" #define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50) @@ -826,23 +868,25 @@ } SK_PNMI_STRUCT_DATA; #define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA)) + +/* The ReturnStatus field must be located before VpdFreeBytes! */ #define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\ &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes)) - /* - * ReturnStatus field - * must be located - * before VpdFreeBytes - */ /* * Various definitions */ +#define SK_PNMI_EVT_TIMER_CHECK 28125000L /* 28125 ms */ + +#define SK_PNMI_VCT_TIMER_CHECK 4000000L /* 4 sec. */ + #define SK_PNMI_MAX_PROTOS 3 -#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum - * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK - * for check while init phase 1 - */ +/* + * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX. + * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO. + */ +#define SK_PNMI_CNT_NO 66 /* * Estimate data structure @@ -856,14 +900,6 @@ /* - * VCT timer data structure - */ -typedef struct s_VctTimer { - SK_TIMER VctTimer; -} SK_PNMI_VCT_TIMER; - - -/* * PNMI specific adapter context structure */ typedef struct s_PnmiPort { @@ -933,9 +969,9 @@ unsigned int TrapQueueEnd; unsigned int TrapBufPad; unsigned int TrapUnique; - SK_U8 VctStatus[SK_MAX_MACS]; - SK_PNMI_VCT VctBackup[SK_MAX_MACS]; - SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS]; + SK_U8 VctStatus[SK_MAX_MACS]; + SK_PNMI_VCT VctBackup[SK_MAX_MACS]; + SK_TIMER VctTimeout[SK_MAX_MACS]; #ifdef SK_DIAG_SUPPORT SK_U32 DiagAttached; #endif /* SK_DIAG_SUPPORT */ diff -ruN linux/drivers/net/sk98lin/h/skgesirq.h linux-new/drivers/net/sk98lin/h/skgesirq.h --- linux/drivers/net/sk98lin/h/skgesirq.h 2004-08-14 12:56:22.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skgesirq.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,22 +2,21 @@ * * Name: skgesirq.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.30 $ - * Date: $Date: 2003/07/04 12:34:13 $ - * Purpose: SK specific Gigabit Ethernet special IRQ functions + * Version: $Revision: 2.3 $ + * Date: $Date: 2004/05/28 14:42:03 $ + * Purpose: Gigabit Ethernet special IRQ functions * ******************************************************************************/ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -44,10 +43,10 @@ #define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */ #define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */ -#define SK_WA_ACT_TIME (5000000UL) /* 5 sec */ -#define SK_WA_INA_TIME (100000UL) /* 100 msec */ +#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */ +#define SK_WA_INA_TIME 100000UL /* 100 msec */ -#define SK_HALFDUP_CHK_TIME (10000UL) /* 10 msec */ +#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */ /* * Define the error numbers and messages @@ -102,10 +101,35 @@ #define SKERR_SIRQ_E024MSG "FIFO overflow error" #define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1) #define SKERR_SIRQ_E025MSG "2 Pair Downshift detected" +#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1) +#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error" +#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1) +#define SKERR_SIRQ_E027MSG "PCI express protocol violation error" +#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1) +#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)" +#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1) +#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)" +#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1) +#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)" +#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1) +#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)" +#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1) +#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1" +#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1) +#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1" +#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1) +#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2" +#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1) +#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2" +#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1) +#define SKERR_SIRQ_E036MSG "CHECK failure polling unit" extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port); extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port); +extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); +extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); #endif /* _INC_SKGESIRQ_H_ */ + diff -ruN linux/drivers/net/sk98lin/h/skgetwsi.h linux-new/drivers/net/sk98lin/h/skgetwsi.h --- linux/drivers/net/sk98lin/h/skgetwsi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-new/drivers/net/sk98lin/h/skgetwsi.h 2004-08-26 10:27:59.000000000 +0200 @@ -0,0 +1,233 @@ +/****************************************************************************** + * + * Name: skgetwsi.h + * Project: Gigabit Ethernet Adapters, TWSI-Module + * Version: $Revision: 1.3 $ + * Date: $Date: 2004/07/29 12:54:31 $ + * Purpose: Special defines for TWSI + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2004 Marvell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/* + * SKGETWSI.H contains all SK-98xx specific defines for the TWSI handling + */ + +#ifndef _INC_SKGETWSI_H_ +#define _INC_SKGETWSI_H_ + +/* + * Macros to access the B2_I2C_CTRL + */ +#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \ + SK_OUT32(IoC, B2_I2C_CTRL,\ + (flag ? 0x80000000UL : 0x0L) | \ + (((SK_U32)reg << 16) & I2C_ADDR) | \ + (((SK_U32)dev << 9) & I2C_DEV_SEL) | \ + (dev_size & I2C_DEV_SIZE) | \ + ((burst << 4) & I2C_BURST_LEN)) + +#define SK_I2C_STOP(IoC) { \ + SK_U32 I2cCtrl; \ + SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \ + SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \ +} + +#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl) + +/* + * Macros to access the TWSI SW Registers + */ +#define SK_I2C_SET_BIT(IoC, SetBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \ +} + +#define SK_I2C_CLR_BIT(IoC, ClrBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \ +} + +#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw) + +/* + * define the possible sensor states + */ +#define SK_SEN_IDLE 0 /* Idle: sensor not read */ +#define SK_SEN_VALUE 1 /* Value Read cycle */ +#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */ + +/* + * Conversion factor to convert read Voltage sensor to milli Volt + * Conversion factor to convert read Temperature sensor to 10th degree Celsius + */ +#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */ +#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */ +#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */ + +/* + * formula: counter = (22500*60)/(rpm * divisor * pulses/2) + * assuming: 6500rpm, 4 pulses, divisor 1 + */ +#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2)) + +/* + * Define sensor management data + * Maximum is reached on Genesis copper dual port and Yukon-64 + * Board specific maximum is in pAC->I2c.MaxSens + */ +#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */ +#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */ + +/* + * To watch the state machine (SM) use the timer in two ways + * instead of one as hitherto + */ +#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */ +#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ + +/* + * Defines for the individual thresholds + */ + +#define C_PLUS_15 1.15 +#define C_PLUS_10 1.10 +#define C_PLUS_5 1.05 +#define C_MINUS_5 0.95 +#define C_MINUS_10 0.90 +#define C_MINUS_15 0.85 + +/* Temperature sensor */ +#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */ +#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */ +#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */ +#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */ + +/* VCC which should be 5 V */ +#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ +#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */ + +/* + * VIO may be 5 V or 3.3 V. Initialization takes two parts: + * 1. Initialize lowest lower limit and highest higher limit. + * 2. After the first value is read correct the upper or the lower limit to + * the appropriate C constant. + * + * Warning limits are +-5% of the exepected voltage. + * Error limits are +-10% of the expected voltage. + */ + +/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */ + +#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */ + /* 5000 mVolt */ +#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */ + +#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */ + +/* correction values for the second pass */ +#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */ + /* 3300 mVolt */ +#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */ + +/* + * VDD voltage + */ +#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */ +#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */ +#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */ +#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */ + +/* + * PHY PLL 3V3 voltage + */ +#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */ +#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */ + +/* + * VAUX (YUKON only) + */ +#define SK_SEN_VAUX_3V3_VAL 3300 /* Voltage VAUX 3.3 Volt */ + +#define SK_SEN_VAUX_3V3_HIGH_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10) +#define SK_SEN_VAUX_3V3_HIGH_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5) +#define SK_SEN_VAUX_3V3_LOW_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5) +#define SK_SEN_VAUX_3V3_LOW_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10) + +#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */ + +/* + * PHY 2V5 voltage + */ +#define SK_SEN_PHY_2V5_VAL 2500 /* Voltage PHY 2.5 Volt */ + +#define SK_SEN_PHY_2V5_HIGH_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10) +#define SK_SEN_PHY_2V5_HIGH_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5) +#define SK_SEN_PHY_2V5_LOW_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5) +#define SK_SEN_PHY_2V5_LOW_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10) + +/* + * ASIC Core 1V5 voltage (YUKON only) + */ +#define SK_SEN_CORE_1V5_VAL 1500 /* Voltage ASIC Core 1.5 Volt */ + +#define SK_SEN_CORE_1V5_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10) +#define SK_SEN_CORE_1V5_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5) +#define SK_SEN_CORE_1V5_LOW_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5) +#define SK_SEN_CORE_1V5_LOW_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10) + +/* + * ASIC Core 1V2 voltage (YUKON-2 only) + */ +#define SK_SEN_CORE_1V2_VAL 1300 /* Voltage ASIC Core 1.3 Volt */ + +#define SK_SEN_CORE_1V2_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15) +#define SK_SEN_CORE_1V2_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_10) +#define SK_SEN_CORE_1V2_LOW_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5) +#define SK_SEN_CORE_1V2_LOW_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10) + +/* + * FAN 1 speed + */ +/* assuming: 6500rpm +-15%, 4 pulses, + * warning at: 80 % + * error at: 70 % + * no upper limit + */ +#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */ +#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */ +#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ +#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */ + +/* + * Some Voltages need dynamic thresholds + */ +#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */ +#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */ +#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */ + +extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#endif /* n_INC_SKGETWSI_H */ + diff -ruN linux/drivers/net/sk98lin/h/ski2c.h linux-new/drivers/net/sk98lin/h/ski2c.h --- linux/drivers/net/sk98lin/h/ski2c.h 2004-08-14 12:55:09.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/ski2c.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,177 +0,0 @@ -/****************************************************************************** - * - * Name: ski2c.h - * Project: Gigabit Ethernet Adapters, TWSI-Module - * Version: $Revision: 1.35 $ - * Date: $Date: 2003/10/20 09:06:30 $ - * Purpose: Defines to access Voltage and Temperature Sensor - * - ******************************************************************************/ - -/****************************************************************************** - * - * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/* - * SKI2C.H contains all I2C specific defines - */ - -#ifndef _SKI2C_H_ -#define _SKI2C_H_ - -typedef struct s_Sensor SK_SENSOR; - -#include "h/skgei2c.h" - -/* - * Define the I2C events. - */ -#define SK_I2CEV_IRQ 1 /* IRQ happened Event */ -#define SK_I2CEV_TIM 2 /* Timeout event */ -#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */ - -/* - * Define READ and WRITE Constants. - */ -#define I2C_READ 0 -#define I2C_WRITE 1 -#define I2C_BURST 1 -#define I2C_SINGLE 0 - -#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0) -#define SKERR_I2C_E001MSG "Sensor index unknown" -#define SKERR_I2C_E002 (SKERR_I2C_E001+1) -#define SKERR_I2C_E002MSG "TWSI: transfer does not complete" -#define SKERR_I2C_E003 (SKERR_I2C_E002+1) -#define SKERR_I2C_E003MSG "LM80: NAK on device send" -#define SKERR_I2C_E004 (SKERR_I2C_E003+1) -#define SKERR_I2C_E004MSG "LM80: NAK on register send" -#define SKERR_I2C_E005 (SKERR_I2C_E004+1) -#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send" -#define SKERR_I2C_E006 (SKERR_I2C_E005+1) -#define SKERR_I2C_E006MSG "Unknown event" -#define SKERR_I2C_E007 (SKERR_I2C_E006+1) -#define SKERR_I2C_E007MSG "LM80 read out of state" -#define SKERR_I2C_E008 (SKERR_I2C_E007+1) -#define SKERR_I2C_E008MSG "Unexpected sensor read completed" -#define SKERR_I2C_E009 (SKERR_I2C_E008+1) -#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range" -#define SKERR_I2C_E010 (SKERR_I2C_E009+1) -#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range" -#define SKERR_I2C_E011 (SKERR_I2C_E010+1) -#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range" -#define SKERR_I2C_E012 (SKERR_I2C_E011+1) -#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range" -#define SKERR_I2C_E013 (SKERR_I2C_E012+1) -#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor" -#define SKERR_I2C_E014 (SKERR_I2C_E013+1) -#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range" -#define SKERR_I2C_E015 (SKERR_I2C_E014+1) -#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range" -#define SKERR_I2C_E016 (SKERR_I2C_E015+1) -#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete" - -/* - * Define Timeout values - */ -#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */ -#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */ -#define SK_I2C_TIM_WATCH 1000000L /* 1 second */ - -/* - * Define trap and error log hold times - */ -#ifndef SK_SEN_ERR_TR_HOLD -#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC) -#endif -#ifndef SK_SEN_ERR_LOG_HOLD -#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC) -#endif -#ifndef SK_SEN_WARN_TR_HOLD -#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC) -#endif -#ifndef SK_SEN_WARN_LOG_HOLD -#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC) -#endif - -/* - * Defines for SenType - */ -#define SK_SEN_UNKNOWN 0 -#define SK_SEN_TEMP 1 -#define SK_SEN_VOLT 2 -#define SK_SEN_FAN 3 - -/* - * Define for the SenErrorFlag - */ -#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */ -#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */ -#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */ -#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */ -#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */ - -/* - * Define the Sensor struct - */ -struct s_Sensor { - char *SenDesc; /* Description */ - int SenType; /* Voltage or Temperature */ - SK_I32 SenValue; /* Current value of the sensor */ - SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */ - SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */ - SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */ - SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */ - int SenErrFlag; /* Sensor indicated an error */ - SK_BOOL SenInit; /* Is sensor initialized ? */ - SK_U64 SenErrCts; /* Error trap counter */ - SK_U64 SenWarnCts; /* Warning trap counter */ - SK_U64 SenBegErrTS; /* Begin error timestamp */ - SK_U64 SenBegWarnTS; /* Begin warning timestamp */ - SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */ - SK_U64 SenLastErrLogTS; /* Last error log timestamp */ - SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */ - SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */ - int SenState; /* Sensor State (see HW specific include) */ - int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen); - /* Sensors read function */ - SK_U16 SenReg; /* Register Address for this sensor */ - SK_U8 SenDev; /* Device Selection for this sensor */ -}; - -typedef struct s_I2c { - SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */ - int CurrSens; /* Which sensor is currently queried */ - int MaxSens; /* Max. number of sensors */ - int TimerMode; /* Use the timer also to watch the state machine */ - int InitLevel; /* Initialized Level */ -#ifndef SK_DIAG - int DummyReads; /* Number of non-checked dummy reads */ - SK_TIMER SenTimer; /* Sensors timer */ -#endif /* !SK_DIAG */ -} SK_I2C; - -extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level); -extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size, - int Reg, int Burst); -extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); -#ifdef SK_DIAG -extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg, - int Burst); -#else /* !SK_DIAG */ -extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); -extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC); -extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC); -#endif /* !SK_DIAG */ -#endif /* n_SKI2C_H */ - diff -ruN linux/drivers/net/sk98lin/h/skqueue.h linux-new/drivers/net/sk98lin/h/skqueue.h --- linux/drivers/net/sk98lin/h/skqueue.h 2004-08-14 12:56:23.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skqueue.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skqueue.h * Project: Gigabit Ethernet Adapters, Event Scheduler Module - * Version: $Revision: 1.16 $ - * Date: $Date: 2003/09/16 12:50:32 $ + * Version: $Revision: 2.3 $ + * Date: $Date: 2004/05/14 13:39:15 $ * Purpose: Defines for the Event queue * ******************************************************************************/ @@ -45,6 +45,9 @@ #define SKGE_RSF 11 /* RSF Aggregation Event Class */ #define SKGE_MARKER 12 /* MARKER Aggregation Event Class */ #define SKGE_FD 13 /* FD Distributor Event Class */ +#ifdef SK_ASF +#define SKGE_ASF 14 /* ASF Event Class */ +#endif /* * define event queue as circular buffer @@ -90,5 +93,11 @@ #define SKERR_Q_E001MSG "Event queue overflow" #define SKERR_Q_E002 (SKERR_Q_E001+1) #define SKERR_Q_E002MSG "Undefined event class" +#define SKERR_Q_E003 (SKERR_Q_E001+2) +#define SKERR_Q_E003MSG "Event queued in Init Level 0" +#define SKERR_Q_E004 (SKERR_Q_E001+3) +#define SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)" +#define SKERR_Q_E005 (SKERR_Q_E001+4) +#define SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1" #endif /* _SKQUEUE_H_ */ diff -ruN linux/drivers/net/sk98lin/h/skrlmt.h linux-new/drivers/net/sk98lin/h/skrlmt.h --- linux/drivers/net/sk98lin/h/skrlmt.h 2004-08-14 12:56:25.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skrlmt.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skrlmt.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.37 $ - * Date: $Date: 2003/04/15 09:43:43 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:09 $ * Purpose: Header file for Redundant Link ManagemenT. * ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/sktimer.h linux-new/drivers/net/sk98lin/h/sktimer.h --- linux/drivers/net/sk98lin/h/sktimer.h 2004-08-14 12:54:51.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/sktimer.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: sktimer.h * Project: Gigabit Ethernet Adapters, Event Scheduler Module - * Version: $Revision: 1.11 $ - * Date: $Date: 2003/09/16 12:58:18 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:09 $ * Purpose: Defines for the timer functions * ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/sktwsi.h linux-new/drivers/net/sk98lin/h/sktwsi.h --- linux/drivers/net/sk98lin/h/sktwsi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-new/drivers/net/sk98lin/h/sktwsi.h 2004-08-26 10:27:59.000000000 +0200 @@ -0,0 +1,177 @@ +/****************************************************************************** + * + * Name: sktwsi.h + * Project: Gigabit Ethernet Adapters, TWSI-Module + * Version: $Revision: 1.1 $ + * Date: $Date: 2003/12/19 14:02:56 $ + * Purpose: Defines to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2003 Marvell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/* + * SKTWSI.H contains all TWSI specific defines + */ + +#ifndef _SKTWSI_H_ +#define _SKTWSI_H_ + +typedef struct s_Sensor SK_SENSOR; + +#include "h/skgetwsi.h" + +/* + * Define the TWSI events. + */ +#define SK_I2CEV_IRQ 1 /* IRQ happened Event */ +#define SK_I2CEV_TIM 2 /* Timeout event */ +#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */ + +/* + * Define READ and WRITE Constants. + */ +#define I2C_READ 0 +#define I2C_WRITE 1 +#define I2C_BURST 1 +#define I2C_SINGLE 0 + +#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0) +#define SKERR_I2C_E001MSG "Sensor index unknown" +#define SKERR_I2C_E002 (SKERR_I2C_E001+1) +#define SKERR_I2C_E002MSG "TWSI: transfer does not complete" +#define SKERR_I2C_E003 (SKERR_I2C_E002+1) +#define SKERR_I2C_E003MSG "LM80: NAK on device send" +#define SKERR_I2C_E004 (SKERR_I2C_E003+1) +#define SKERR_I2C_E004MSG "LM80: NAK on register send" +#define SKERR_I2C_E005 (SKERR_I2C_E004+1) +#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send" +#define SKERR_I2C_E006 (SKERR_I2C_E005+1) +#define SKERR_I2C_E006MSG "Unknown event" +#define SKERR_I2C_E007 (SKERR_I2C_E006+1) +#define SKERR_I2C_E007MSG "LM80 read out of state" +#define SKERR_I2C_E008 (SKERR_I2C_E007+1) +#define SKERR_I2C_E008MSG "Unexpected sensor read completed" +#define SKERR_I2C_E009 (SKERR_I2C_E008+1) +#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range" +#define SKERR_I2C_E010 (SKERR_I2C_E009+1) +#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range" +#define SKERR_I2C_E011 (SKERR_I2C_E010+1) +#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range" +#define SKERR_I2C_E012 (SKERR_I2C_E011+1) +#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range" +#define SKERR_I2C_E013 (SKERR_I2C_E012+1) +#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor" +#define SKERR_I2C_E014 (SKERR_I2C_E013+1) +#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range" +#define SKERR_I2C_E015 (SKERR_I2C_E014+1) +#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range" +#define SKERR_I2C_E016 (SKERR_I2C_E015+1) +#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete" + +/* + * Define Timeout values + */ +#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */ +#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */ +#define SK_I2C_TIM_WATCH 1000000L /* 1 second */ + +/* + * Define trap and error log hold times + */ +#ifndef SK_SEN_ERR_TR_HOLD +#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_ERR_LOG_HOLD +#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_TR_HOLD +#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_LOG_HOLD +#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC) +#endif + +/* + * Defines for SenType + */ +#define SK_SEN_UNKNOWN 0 +#define SK_SEN_TEMP 1 +#define SK_SEN_VOLT 2 +#define SK_SEN_FAN 3 + +/* + * Define for the SenErrorFlag + */ +#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */ +#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */ +#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */ +#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */ +#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */ + +/* + * Define the Sensor struct + */ +struct s_Sensor { + char *SenDesc; /* Description */ + int SenType; /* Voltage or Temperature */ + SK_I32 SenValue; /* Current value of the sensor */ + SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */ + SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */ + SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */ + SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */ + int SenErrFlag; /* Sensor indicated an error */ + SK_BOOL SenInit; /* Is sensor initialized ? */ + SK_U64 SenErrCts; /* Error trap counter */ + SK_U64 SenWarnCts; /* Warning trap counter */ + SK_U64 SenBegErrTS; /* Begin error timestamp */ + SK_U64 SenBegWarnTS; /* Begin warning timestamp */ + SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */ + SK_U64 SenLastErrLogTS; /* Last error log timestamp */ + SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */ + SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */ + int SenState; /* Sensor State (see HW specific include) */ + int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen); + /* Sensors read function */ + SK_U16 SenReg; /* Register Address for this sensor */ + SK_U8 SenDev; /* Device Selection for this sensor */ +}; + +typedef struct s_I2c { + SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */ + int CurrSens; /* Which sensor is currently queried */ + int MaxSens; /* Max. number of sensors */ + int TimerMode; /* Use the timer also to watch the state machine */ + int InitLevel; /* Initialized Level */ +#ifndef SK_DIAG + int DummyReads; /* Number of non-checked dummy reads */ + SK_TIMER SenTimer; /* Sensors timer */ +#endif /* !SK_DIAG */ +} SK_I2C; + +extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level); +extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size, + int Reg, int Burst); +extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#ifdef SK_DIAG +extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg, + int Burst); +#else /* !SK_DIAG */ +extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); +extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC); +extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC); +#endif /* !SK_DIAG */ +#endif /* n_SKTWSI_H */ + diff -ruN linux/drivers/net/sk98lin/h/sktypes.h linux-new/drivers/net/sk98lin/h/sktypes.h --- linux/drivers/net/sk98lin/h/sktypes.h 2004-08-14 12:56:24.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/sktypes.h 2004-08-26 10:27:59.000000000 +0200 @@ -3,7 +3,7 @@ * Name: sktypes.h * Project: GEnesis, PCI Gigabit Ethernet Adapter * Version: $Revision: 1.2 $ - * Date: $Date: 2003/10/07 08:16:51 $ + * Date: $Date: 2004/07/09 13:29:49 $ * Purpose: Define data types for Linux * ******************************************************************************/ @@ -22,48 +22,28 @@ * ******************************************************************************/ -/****************************************************************************** - * - * Description: - * - * In this file, all data types that are needed by the common modules - * are mapped to Linux data types. - * - * - * Include File Hierarchy: - * - * - ******************************************************************************/ - #ifndef __INC_SKTYPES_H #define __INC_SKTYPES_H - -/* defines *******************************************************************/ - -/* - * Data types with a specific size. 'I' = signed, 'U' = unsigned. - */ -#define SK_I8 s8 -#define SK_U8 u8 -#define SK_I16 s16 -#define SK_U16 u16 -#define SK_I32 s32 -#define SK_U32 u32 -#define SK_I64 s64 -#define SK_U64 u64 - -#define SK_UPTR ulong /* casting pointer <-> integral */ - -/* -* Boolean type. -*/ -#define SK_BOOL SK_U8 -#define SK_FALSE 0 -#define SK_TRUE (!SK_FALSE) - -/* typedefs *******************************************************************/ - -/* function prototypes ********************************************************/ +#define SK_I8 s8 /* 8 bits (1 byte) signed */ +#define SK_U8 u8 /* 8 bits (1 byte) unsigned */ +#define SK_I16 s16 /* 16 bits (2 bytes) signed */ +#define SK_U16 u16 /* 16 bits (2 bytes) unsigned */ +#define SK_I32 s32 /* 32 bits (4 bytes) signed */ +#define SK_U32 u32 /* 32 bits (4 bytes) unsigned */ +#define SK_I64 s64 /* 64 bits (8 bytes) signed */ +#define SK_U64 u64 /* 64 bits (8 bytes) unsigned */ + +#define SK_UPTR ulong /* casting pointer <-> integral */ + +#define SK_BOOL SK_U8 +#define SK_FALSE 0 +#define SK_TRUE (!SK_FALSE) #endif /* __INC_SKTYPES_H */ + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skversion.h linux-new/drivers/net/sk98lin/h/skversion.h --- linux/drivers/net/sk98lin/h/skversion.h 2004-08-14 12:55:33.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skversion.h 2004-08-26 10:27:59.000000000 +0200 @@ -1,17 +1,17 @@ /****************************************************************************** * - * Name: version.h + * Name: skversion.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.5 $ - * Date: $Date: 2003/10/07 08:16:51 $ - * Purpose: SK specific Error log support + * Version: $Revision: 1.3 $ + * Date: $Date: 2004/07/09 13:33:59 $ + * Purpose: specific version strings and numbers * ******************************************************************************/ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect GmbH. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,17 +22,15 @@ * ******************************************************************************/ -#ifdef lint -static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH."; -static const char SysKonnectBuildNumber[] = - "@(#)SK-BUILD: 6.23 PL: 01"; -#endif /* !defined(lint) */ - -#define BOOT_STRING "sk98lin: Network Device Driver v6.23\n" \ - "(C)Copyright 1999-2004 Marvell(R)." - -#define VER_STRING "6.23" -#define DRIVER_FILE_NAME "sk98lin" -#define DRIVER_REL_DATE "Feb-13-2004" - +#define BOOT_STRING "sk98lin: Network Device Driver v7.07\n" \ + "(C)Copyright 1999-2004 Marvell(R)." +#define VER_STRING "7.07" +#define PATCHLEVEL "01" +#define DRIVER_FILE_NAME "sk98lin" +#define DRIVER_REL_DATE "Aug-26-2004" +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skvpd.h linux-new/drivers/net/sk98lin/h/skvpd.h --- linux/drivers/net/sk98lin/h/skvpd.h 2004-08-14 12:55:10.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/skvpd.h 2004-08-26 10:27:59.000000000 +0200 @@ -1,22 +1,22 @@ /****************************************************************************** * * Name: skvpd.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.15 $ - * Date: $Date: 2003/01/13 10:39:38 $ + * Project: Gigabit Ethernet Adapters, VPD-Module + * Version: $Revision: 2.5 $ + * Date: $Date: 2004/08/11 14:36:16 $ * Purpose: Defines and Macros for VPD handling * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -48,6 +48,8 @@ #define VPD_YA "YA" /* Asset Tag Identifier */ #define VPD_VL "VL" /* First Error Log Message (SK specific) */ #define VPD_VF "VF" /* Second Error Log Message (SK specific) */ +#define VPD_VB "VB" /* Boot Agent ROM Configuration (SK specific) */ +#define VPD_VE "VE" /* EFI UNDI Configuration (SK specific) */ #define VPD_RW "RW" /* Remaining Read / Write Area */ /* 'type' values for vpd_setup_para() */ @@ -135,49 +137,49 @@ #define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal) #define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal) #else /* VPD_DO_IO */ -#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val) -#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val) -#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(Addr),Val) -#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal) -#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal) -#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal) +#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(pAC,Addr),Val) +#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(pAC,Addr),Val) +#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(pAC,Addr),Val) +#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(pAC,Addr),pVal) +#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(pAC,Addr),pVal) +#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(pAC,Addr),pVal) #endif /* VPD_DO_IO */ #else /* SKDIAG */ #define VPD_OUT8(pAC,Ioc,Addr,Val) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgByte(pAC,Addr,Val); \ else \ - SK_OUT8(pAC,PCI_C(Addr),Val); \ + SK_OUT8(pAC,PCI_C(pAC,Addr),Val); \ } #define VPD_OUT16(pAC,Ioc,Addr,Val) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgWord(pAC,Addr,Val); \ else \ - SK_OUT16(pAC,PCI_C(Addr),Val); \ + SK_OUT16(pAC,PCI_C(pAC,Addr),Val); \ } #define VPD_OUT32(pAC,Ioc,Addr,Val) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgDWord(pAC,Addr,Val); \ else \ - SK_OUT32(pAC,PCI_C(Addr),Val); \ + SK_OUT32(pAC,PCI_C(pAC,Addr),Val); \ } #define VPD_IN8(pAC,Ioc,Addr,pVal) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgByte(pAC,Addr,pVal); \ else \ - SK_IN8(pAC,PCI_C(Addr),pVal); \ + SK_IN8(pAC,PCI_C(pAC,Addr),pVal); \ } #define VPD_IN16(pAC,Ioc,Addr,pVal) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgWord(pAC,Addr,pVal); \ else \ - SK_IN16(pAC,PCI_C(Addr),pVal); \ + SK_IN16(pAC,PCI_C(pAC,Addr),pVal); \ } #define VPD_IN32(pAC,Ioc,Addr,pVal) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgDWord(pAC,Addr,pVal); \ else \ - SK_IN32(pAC,PCI_C(Addr),pVal); \ + SK_IN32(pAC,PCI_C(pAC,Addr),pVal); \ } #endif /* nSKDIAG */ @@ -240,7 +242,12 @@ SK_IOC IoC, char *msg); -#ifdef SKDIAG +int VpdInit( + SK_AC *pAC, + SK_IOC IoC); + +#if defined(SKDIAG) || defined(SK_ASF) + extern int VpdReadBlock( SK_AC *pAC, SK_IOC IoC, @@ -254,7 +261,9 @@ char *buf, int addr, int len); -#endif /* SKDIAG */ + +#endif /* SKDIAG || SK_ASF */ + #else /* SK_KR_PROTO */ extern SK_U32 VpdReadDWord(); extern int VpdSetupPara(); diff -ruN linux/drivers/net/sk98lin/h/sky2le.h linux-new/drivers/net/sk98lin/h/sky2le.h --- linux/drivers/net/sk98lin/h/sky2le.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-new/drivers/net/sk98lin/h/sky2le.h 2004-08-26 10:27:59.000000000 +0200 @@ -0,0 +1,872 @@ +/****************************************************************************** + * + * Name: sky2le.h + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 1.7 $ + * Date: $Date: 2004/03/04 14:20:51 $ + * Purpose: Common list element definitions and access macros. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 2003 Marvell. + * All Rights Reserved + * + * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL + * The copyright notice above does not evidence any + * actual or intended publication of such source code. + * + * This Module contains Proprietary Information of Marvell + * and should be treated as Confidential. + * + * The information in this file is provided for the exclusive use of + * the licensees of Marvell. + * Such users have the right to use, modify, and incorporate this code + * into products for purposes authorized by the license agreement + * provided they include this notice and the associated copyright notice + * with any such product. + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +#ifndef __INC_SKY2LE_H +#define __INC_SKY2LE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/* defines ********************************************************************/ + +#define MIN_LEN_OF_LE_TAB 128 +#define MAX_LEN_OF_LE_TAB 4096 +#ifdef USE_POLLING_UNIT +#define NUM_LE_POLLING_UNIT 2 +#endif +#define MAX_FRAG_OVERHEAD 10 + +/* Macro for aligning a given value */ +#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) { \ + (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1))); \ +} + +/****************************************************************************** + * + * LE2DWord() - Converts the given Little Endian value to machine order value + * + * Description: + * This function converts the Little Endian value received as an argument to + * the machine order value. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN + +#define LE2DWord(value) (value) + +#else /* !SK_LITTLE_ENDIAN */ + +#define LE2DWord(value) \ + ((((value)<<24L)&0xff000000L) + \ + (((value)<< 8L)&0x00ff0000L) + \ + (((value)>> 8L)&0x0000ff00L) + \ + (((value)>>24L)&0x000000ffL)) + +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * DWord2LE() - Converts the given value to a Little Endian value + * + * Description: + * This function converts the value received as an argument to a Little Endian + * value on Big Endian machines. If the machine running the code is Little + * Endian, then no conversion is done. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN + +#define DWord2LE(value) (value) + +#else /* !SK_LITTLE_ENDIAN */ + +#define DWord2LE(value) \ + ((((value)<<24L)&0xff000000L) + \ + (((value)<< 8L)&0x00ff0000L) + \ + (((value)>> 8L)&0x0000ff00L) + \ + (((value)>>24L)&0x000000ffL)) + +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * LE2Word() - Converts the given Little Endian value to machine order value + * + * Description: + * This function converts the Little Endian value received as an argument to + * the machine order value. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN + +#define LE2Word(value) (value) + +#else /* !SK_LITTLE_ENDIAN */ + +#define LE2Word(value) \ + ((((value)<< 8L)&0xff00) + \ + (((value)>> 8L)&0x00ff)) + +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * Word2LE() - Converts the given value to a Little Endian value + * + * Description: + * This function converts the value received as an argument to a Little Endian + * value on Big Endian machines. If the machine running the code is Little + * Endian, then no conversion is done. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN + +#define Word2LE(value) (value) + +#else /* !SK_LITTLE_ENDIAN */ + +#define Word2LE(value) \ + ((((value)<< 8L)&0xff00) + \ + (((value)>> 8L)&0x00ff)) + +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * Transmit list element macros + * + */ + +#define TXLE_SET_ADDR(pLE, Addr) \ + ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr)) +#define TXLE_SET_LSLEN(pLE, Len) \ + ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len)) +#define TXLE_SET_STACS(pLE, Start) \ + ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start)) +#define TXLE_SET_WRICS(pLE, Write) \ + ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write)) +#define TXLE_SET_INICS(pLE, Ini) ((pLE)->Tx.Send.InitCsum = Word2LE(Ini)) +#define TXLE_SET_LEN(pLE, Len) ((pLE)->Tx.Send.BufLen = Word2LE(Len)) +#define TXLE_SET_VLAN(pLE, Vlan) ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan)) +#define TXLE_SET_LCKCS(pLE, Lock) ((pLE)->Tx.ControlFlags = (Lock)) +#define TXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Tx.ControlFlags = (Ctrl)) +#define TXLE_SET_OPC(pLE, Opc) ((pLE)->Tx.Opcode = (Opc)) + + +#define TXLE_GET_ADDR(pLE) LE2DWord((pLE)->Tx.TxUn.BufAddr) +#define TXLE_GET_LSLEN(pLE) LE2Word((pLE)->Tx.TxUn.LargeSend.Length) +#define TXLE_GET_STACS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp) +#define TXLE_GET_WRICS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp) +#define TXLE_GET_INICS(pLE) LE2Word((pLE)->Tx.Send.InitCsum) +#define TXLE_GET_LEN(pLE) LE2Word((pLE)->Tx.Send.BufLen) +#define TXLE_GET_VLAN(pLE) LE2Word((pLE)->Tx.Send.VlanTag) +#define TXLE_GET_LCKCS(pLE) ((pLE)->Tx.ControlFlags) +#define TXLE_GET_CTRL(pLE) ((pLE)->Tx.ControlFlags) +#define TXLE_GET_OPC(pLE) ((pLE)->Tx.Opcode) + +/****************************************************************************** + * + * Receive list element macros + * + */ + +#define RXLE_SET_ADDR(pLE, Addr) \ + ((pLE)->Rx.RxUn.BufAddr = (SK_U32) DWord2LE(Addr)) +#define RXLE_SET_STACS2(pLE, Offs) \ + ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs)) +#define RXLE_SET_STACS1(pLE, Offs) \ + ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs)) +#define RXLE_SET_LEN(pLE, Len) ((pLE)->Rx.BufferLength = Word2LE(Len)) +#define RXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Rx.ControlFlags = (Ctrl)) +#define RXLE_SET_OPC(pLE, Opc) ((pLE)->Rx.Opcode = (Opc)) + + +#define RXLE_GET_ADDR(pLE) LE2DWord((pLE)->Rx.RxUn.BufAddr) +#define RXLE_GET_STACS2(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2) +#define RXLE_GET_STACS1(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1) +#define RXLE_GET_LEN(pLE) LE2Word((pLE)->Rx.BufferLength) +#define RXLE_GET_CTRL(pLE) ((pLE)->Rx.ControlFlags) +#define RXLE_GET_OPC(pLE) ((pLE)->Rx.Opcode) + +/****************************************************************************** + * + * Status list element macros + * + */ + +#define STLE_SET_OPC(pLE, Opc) ((pLE)->St.Opcode = (Opc)) + +#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord) +#define STLE_GET_TIST(pLE) LE2DWord((pLE)->St.StUn.StRxTimeStamp) +#define STLE_GET_TCP1(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1) +#define STLE_GET_TCP2(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2) +#define STLE_GET_LEN(pLE) LE2Word((pLE)->St.Stat.BufLen) +#define STLE_GET_VLAN(pLE) LE2Word((pLE)->St.Stat.VlanTag) +#define STLE_GET_LINK(pLE) ((pLE)->St.Link) +#define STLE_GET_OPC(pLE) ((pLE)->St.Opcode) +#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) { \ + (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow); \ + (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi); \ +} + +#define STLE_GET_RSS(pLE) LE2DWord((pLE)->St.StUn.StRxRssValue) +#define STLE_GET_IPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG) +#define STLE_GET_TCPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG) + + +/* I always take both values as a paramter to avoid typos */ +#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal) \ + (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL) +#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal) \ + ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL) +#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal) \ + (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) + \ + ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH)) +#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal) \ + ((HighVal & STLE_TXS2_MSKL) >> STLE_TXS2_SHIFTL) + + +#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) { \ + (IsOk) = (((RxStat) & GMR_FS_RX_OK) == GMR_FS_RX_OK) && \ + (((RxStat) & GMR_FS_ANY_ERR) == 0); \ + \ + if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >> \ + GMR_FS_LEN_SHIFT) != (Len))) { \ + /* length in MAC status differs from length in LE */ \ + (IsOk) = SK_FALSE; \ + } \ +} + + +/****************************************************************************** + * + * Polling unit list element macros + * + * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid + * + */ + +#ifdef USE_POLLING_UNIT + +#define POLE_SET_OPC(pLE, Opc) ((pLE)->Sa.Opcode = (Opc)) +#define POLE_SET_LINK(pLE, Port) ((pLE)->Sa.Link = (Port)) +#define POLE_SET_RXIDX(pLE, Idx) ((pLE)->Sa.RxIdxVld = Word2LE(Idx)) +#define POLE_SET_TXAIDX(pLE, Idx) ((pLE)->Sa.TxAIdxVld = Word2LE(Idx)) +#define POLE_SET_TXSIDX(pLE, Idx) ((pLE)->Sa.TxSIdxVld = Word2LE(Idx)) + +#define POLE_GET_OPC(pLE) ((pLE)->Sa.Opcode) +#define POLE_GET_LINK(pLE) ((pLE)->Sa.Link) +#define POLE_GET_RXIDX(pLE) LE2Word((pLE)->Sa.RxIdxVld) +#define POLE_GET_TXAIDX(pLE) LE2Word((pLE)->Sa.TxAIdxVld) +#define POLE_GET_TXSIDX(pLE) LE2Word((pLE)->Sa.TxSIdxVld) + +#endif /* USE_POLLING_UNIT */ + +/****************************************************************************** + * + * Debug macros for list elements + * + */ + +#ifdef DEBUG + +#define SK_DBG_DUMP_RX_LE(pLE) { \ + SK_U8 Opcode; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = RXLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x ",Opcode)); \ + switch (Opcode & (~HW_OWNER)) { \ + case OP_BUFFER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_BUFFER\n")); \ + break; \ + case OP_PACKET: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_PACKET\n")); \ + break; \ + case OP_ADDR64: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_ADDR64\n")); \ + break; \ + case OP_TCPSTART: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPPAR\n")); \ + break; \ + case SW_OWNER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunused LE\n")); \ + break; \ + default: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown Opcode!!!\n")); \ + break; \ + } \ + if ((Opcode & OP_BUFFER) == OP_BUFFER) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_ADDR64) == OP_ADDR64) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE))); \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} + +#define SK_DBG_DUMP_TX_LE(pLE) { \ + SK_U8 Opcode; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = TXLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x ",Opcode)); \ + switch (Opcode & (~HW_OWNER)) { \ + case OP_TCPCHKSUM: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPCHKSUM\n")); \ + break; \ + case OP_TCPIS: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPIS\n")); \ + break; \ + case OP_TCPLCK: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLCK\n")); \ + break; \ + case OP_TCPLW: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLW\n")); \ + break; \ + case OP_TCPLSW: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLSW\n")); \ + break; \ + case OP_TCPLISW: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLISW\n")); \ + break; \ + case OP_ADDR64: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_ADDR64\n")); \ + break; \ + case OP_VLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_VLAN\n")); \ + break; \ + case OP_ADDR64VLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_ADDR64VLAN\n")); \ + break; \ + case OP_LRGLEN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_LRGLEN\n")); \ + break; \ + case OP_LRGLENVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_LRGLENVLAN\n")); \ + break; \ + case OP_BUFFER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_BUFFER\n")); \ + break; \ + case OP_PACKET: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_PACKET\n")); \ + break; \ + case OP_LARGESEND: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_LARGESEND\n")); \ + break; \ + case SW_OWNER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunused LE\n")); \ + break; \ + default: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown Opcode!!!\n")); \ + break; \ + } \ + if ((Opcode & OP_BUFFER) == OP_BUFFER) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_ADDR64) == OP_ADDR64) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_VLAN) == OP_VLAN) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE))); \ + } \ + if ((Opcode & OP_LRGLEN) == OP_LRGLEN) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE))); \ + } \ + if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) { \ + if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE))); \ + } \ + if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE))); \ + } \ + if ((Opcode & OP_TCPINIT) == OP_TCPINIT) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE))); \ + } \ + if ((Opcode & OP_TCPLCK) == OP_TCPLCK) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE))); \ + } \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} + +#define SK_DBG_DUMP_ST_LE(pLE) { \ + SK_U8 Opcode; \ + SK_U16 HighVal; \ + SK_U32 LowVal; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = STLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x", Opcode)); \ + Opcode &= (~HW_OWNER); \ + switch (Opcode) { \ + case OP_RXSTAT: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXSTAT\n")); \ + break; \ + case OP_RXTIMESTAMP: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXTIMESTAMP\n")); \ + break; \ + case OP_RXVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXVLAN\n")); \ + break; \ + case OP_RXCHKS: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXCHKS\n")); \ + break; \ + case OP_RXCHKSVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXCHKSVLAN\n")); \ + break; \ + case OP_RXTIMEVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXTIMEVLAN\n")); \ + break; \ + case OP_RSS_HASH: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RSS_HASH\n")); \ + break; \ + case OP_TXINDEXLE: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TXINDEXLE\n")); \ + break; \ + case HW_OWNER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunused LE\n")); \ + break; \ + default: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown status list element!!!\n")); \ + break; \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE))); \ + if (Opcode == OP_RXSTAT) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE))); \ + } \ + if ((Opcode & OP_RXVLAN) == OP_RXVLAN) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE))); \ + } \ + if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE))); \ + } \ + if ((Opcode & OP_RXCHKS) == OP_RXCHKS) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE), \ + STLE_GET_TCP2(pLE))); \ + } \ + if (Opcode == OP_TXINDEXLE) { \ + STLE_GET_DONE_IDX(pLE, LowVal, HighVal); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxA1: 0x%x\n", \ + STLE_GET_DONE_IDX_TXA1(LowVal,HighVal))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxS1: 0x%x\n", \ + STLE_GET_DONE_IDX_TXS1(LowVal,HighVal))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxA2: 0x%x\n", \ + STLE_GET_DONE_IDX_TXA2(LowVal,HighVal))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxS2: 0x%x\n", \ + STLE_GET_DONE_IDX_TXS2(LowVal,HighVal))); \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} + +#ifdef USE_POLLING_UNIT +#define SK_DBG_DUMP_PO_LE(pLE) { \ + SK_U8 Opcode; \ + SK_U16 Idx; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = POLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x ",Opcode)); \ + if ((Opcode & ~HW_OWNER) == OP_PUTIDX) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_PUTIDX\n")); \ + } \ + else { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown Opcode!!!\n")); \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE))); \ + Idx = POLE_GET_TXAIDX(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTxA Index is 0x%X and %svalid\n", Idx, \ + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \ + Idx = POLE_GET_TXSIDX(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTxS Index is 0x%X and %svalid\n", Idx, \ + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \ + Idx = POLE_GET_RXIDX(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tRx Index is 0x%X and %svalid\n", Idx, \ + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} +#endif /* USE_POLLING_UNIT */ + +#else /* !DEBUG */ + +#define SK_DBG_DUMP_RX_LE(pLE) +#define SK_DBG_DUMP_TX_LE(pLE) +#define SK_DBG_DUMP_ST_LE(pLE) +#define SK_DBG_DUMP_PO_LE(pLE) + +#endif /* !DEBUG */ + +/****************************************************************************** + * + * Macros for listelement tables + * + * + */ + +#define LE_SIZE sizeof(SK_HWLE) +#define LE_TAB_SIZE(NumElements) ((NumElements) * LE_SIZE) + +/* Number of unused list elements in table + * this macro always returns the number of free listelements - 1 + * this way we want to guarantee that always one LE remains unused + */ +#define NUM_FREE_LE_IN_TABLE(pTable) \ + ( ((pTable)->Put >= (pTable)->Done) ? \ + (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) : \ + ((pTable)->Done - (pTable)->Put - 1) ) + +/* total number of list elements in table */ +#define NUM_LE_IN_TABLE(pTable) ((pTable)->Num) + +/* get next unused rx list element */ +#define GET_RX_LE(pLE, pTable) { \ + pLE = &(pTable)->pLETab[(pTable)->Put]; \ + (pTable)->Put = ((pTable)->Put + 1) % NUM_LE_IN_TABLE(pTable); \ +} + +/* get next unused tx list element */ +#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable) + +/* get next status list element expected to be finished by hw */ +#define GET_ST_LE(pLE, pTable) { \ + pLE = &(pTable)->pLETab[(pTable)->Done]; \ + (pTable)->Done = ((pTable)->Done +1) % NUM_LE_IN_TABLE(pTable); \ +} + +#ifdef USE_POLLING_UNIT +/* get next polling unit list element for port */ +#define GET_PO_LE(pLE, pTable, Port) { \ + pLE = &(pTable)->pLETab[(Port)]; \ +} +#endif /* USE_POLLING_UNIT */ + +#define GET_PUT_IDX(pTable) ((pTable)->Put) + +#define UPDATE_HWPUT_IDX(pTable) {(pTable)->HwPut = (pTable)->Put; } + +/* + * get own bit of next status LE + * if the result is != 0 there has been at least one status LE finished + */ +#define OWN_OF_FIRST_LE(pTable) \ + (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER) + +#define SET_DONE_INDEX(pTable, Idx) (pTable)->Done = (Idx); + +#define GET_DONE_INDEX(pTable) ((pTable)->Done) + +#ifdef SAFE_BUT_SLOW + +/* check own bit of LE before current done idx */ +#define CHECK_STLE_OVERFLOW(pTable, IsOk) { \ + unsigned i; \ + if ((i = (pTable)->Done) == 0) { \ + i = NUM_LE_IN_TABLE(pTable); \ + } \ + else { \ + i = i - 1; \ + } \ + if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) { \ + (IsOk) = SK_TRUE; \ + } \ + else { \ + (IsOk) = SK_FALSE; \ + } \ + } + + +/* + * for Yukon2 the hardware is not polling the list elements, so it + * is not necessary to change the own-bit of rx or tx-LEs before + * reusing them + * but it might make debugging easier if one simply can see whether + * a LE has been worked on + */ + +#define CLEAR_LE_OWN(pTable, Idx) \ + STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER) + +/* + * clear all own bits starting from old done index up to the LE before + * the new done index + */ +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) { \ + int i; \ + i = (pTable)->Done; \ + while (i != To) { \ + CLEAR_LE_OWN(pTable, i); \ + i = (i + 1) % NUM_LE_IN_TABLE(pTable); \ + } \ + } + +#else /* !SAFE_BUT_SLOW */ + +#define CHECK_STLE_OVERFLOW(pTable, IsOk) +#define CLEAR_LE_OWN(pTable, Idx) +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) + +#endif /* !SAFE_BUT_SLOW */ + + +/* typedefs *******************************************************************/ + +typedef struct s_LetRxTx { + SK_U16 VlanId; /* VLAN Id given down last time */ + SK_U16 TcpWp; /* TCP Checksum Write Position */ + SK_U16 TcpSp1; /* TCP Checksum Calculation Start Position 1 */ + SK_U16 TcpSp2; /* TCP Checksum Calculation Start Position 2 */ + SK_U16 MssValue; /* Maximum Segment Size */ + SK_U16 Reserved1; /* reserved word for furture extensions */ + SK_U16 Reserved2; /* reserved word for furture extensions */ + SK_U16 Reserved3; /* reserved word for furture extensions */ +} SK_LET_RX_TX; + +typedef struct s_LetStat { + SK_U32 RxTimeStamp; /* Receive Timestamp */ + SK_U32 RssHashValue; /* RSS Hash Value */ + SK_BOOL RssIsIp; /* RSS Hash Value: IP packet detected */ + SK_BOOL RssIsTcp; /* RSS Hash Value: IP+TCP packet detected */ + SK_U16 VlanId; /* VLAN Id given received by Status BMU */ + SK_U16 TcpSum1; /* TCP checksum 1 (status BMU) */ + SK_U16 TcpSum2; /* TCP checksum 2 (status BMU) */ +} SK_LET_STAT; + + +typedef union s_LetBmuSpec { + SK_LET_RX_TX RxTx; /* Rx/Tx BMU specific variables */ + SK_LET_STAT Stat; /* Status BMU specific variables */ +} SK_LET_BMU_S; + + + +typedef struct s_le_table SK_LE_TABLE; + +struct s_le_table { + /* all LE's between Done and HWPut are owned by the hardware */ + /* all LE's between Put and Done can be used from Software */ + /* all LE's between HWPut and Put are currently processed in DriverSend */ + unsigned Done; /* done index - consumed from HW and available */ + unsigned Put; /* put index - to be given to hardware */ + unsigned HwPut; /* put index actually given to hardware */ + unsigned Num; /* total number of list elements */ + SK_HWLE *pLETab; /* virtual address of list element table */ + SK_U32 pPhyLETABLow; /* physical address of list element table */ + SK_U32 pPhyLETABHigh; /* physical address of list element table */ + /* values to remember in order to save some LEs */ + SK_U32 BufHighAddr; /* high addr given down last time */ + SK_LET_BMU_S Bmu; /* contains BMU specific information */ + SK_U32 private; /* driver private variable free usable */ + SK_U16 TcpInitCsum; /* Init. Checksum */ +}; + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO + +/* + * public functions in sky2le.c + */ +extern void SkGeY2SetPutIndex( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 StartAddrPrefetchUnit, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitPrefetchUnit( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Queue, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitStatBmu( + SK_AC *pAC, + SK_IOC IoC, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitPollUnit( + SK_AC *pAC, + SK_IOC IoC, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitSingleLETable( + SK_AC *pAC, + SK_LE_TABLE *pLETab, + unsigned int NumLE, + void *pVMem, + SK_U32 PMemLowAddr, + SK_U32 PMemHighAddr); + +#else /* SK_KR_PROTO */ +extern void SkGeY2SetPutIndex(); +extern void SkGeY2InitPrefetchUnit(); +extern void SkGeY2InitStatBmu(); +extern void SkGeY2InitPollUnit(); +extern void SkGeY2InitSingleLETable(); +#endif /* SK_KR_PROTO */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKY2LE_H */ + diff -ruN linux/drivers/net/sk98lin/h/xmac_ii.h linux-new/drivers/net/sk98lin/h/xmac_ii.h --- linux/drivers/net/sk98lin/h/xmac_ii.h 2004-08-14 12:56:00.000000000 +0200 +++ linux-new/drivers/net/sk98lin/h/xmac_ii.h 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: xmac_ii.h * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.52 $ - * Date: $Date: 2003/10/02 16:35:50 $ + * Version: $Revision: 2.7 $ + * Date: $Date: 2004/07/02 15:01:01 $ * Purpose: Defines and Macros for Gigabit Ethernet Controller * ******************************************************************************/ @@ -11,13 +11,12 @@ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -449,7 +448,7 @@ /* * Receive Frame Status Encoding */ -#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ +#define XMR_FS_LEN_MSK (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ #define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/ #define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/ #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */ @@ -469,6 +468,8 @@ #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */ #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */ +#define XMR_FS_LEN_SHIFT 18 + /* * XMR_FS_ERR will be set if * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, @@ -510,7 +511,7 @@ #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */ #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* Broadcom-specific registers */ -#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ /* 0x0b - 0x0e: reserved */ #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ @@ -541,7 +542,7 @@ #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* Marvel-specific registers */ -#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ /* 0x0b - 0x0e: reserved */ #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ @@ -552,13 +553,21 @@ #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ - /* 0x17: reserved */ +#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ - /* 0x1d - 0x1f: reserved */ +#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ +#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ + +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ +#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ +#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ +#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ +#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ /*----------------------------------------------------------------------------*/ /* @@ -574,7 +583,7 @@ #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */ #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* Level One-specific registers */ -#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/ +#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ /* 0x0b -0x0e: reserved */ #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ @@ -618,7 +627,7 @@ /* * PHY bit definitions - * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are + * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are * XMAC/Broadcom/LevelOne/National/Marvell-specific. * All other are general. */ @@ -629,14 +638,14 @@ /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/ #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ -#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */ +#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ -#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */ -#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */ +#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ +#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ -#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */ -#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */ +#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ +#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ /* Bit 5..0: reserved */ #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ @@ -649,15 +658,15 @@ /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/ /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/ /* Bit 15..9: reserved */ - /* (BC/L1) 100/10 Mbps cap bits ignored*/ + /* (BC/L1) 100/10 Mbps cap bits ignored */ #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ /* Bit 7: reserved */ -#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */ +#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ -#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */ +#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ @@ -667,7 +676,7 @@ /***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */ #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ -#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */ +#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ /* different Broadcom PHY Ids */ #define PHY_BCOM_ID1_A1 0x6041 @@ -981,7 +990,7 @@ #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */ #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */ #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */ -#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */ +#define PHY_L_QS_LLE (7<<4) /* Bit 6..4: Line Length Estim. */ #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */ #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */ #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */ @@ -1029,9 +1038,8 @@ /* Bit 9..0: not described */ /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/ -#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */ -#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */ - +#define PHY_L_CIM_ISOL (0xff<<8) /* Bit 15..8: Isolate Count */ +#define PHY_L_CIM_FALSE_CAR 0xff /* Bit 7..0: False Carrier Count */ /* * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding @@ -1041,7 +1049,6 @@ #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ - /* * National-Specific */ @@ -1086,22 +1093,24 @@ */ /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ -#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ -#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ -#define PHY_M_AN_RF BIT_13 /* Remote Fault */ - /* Bit 12: reserved */ -#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ -#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ -#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ -#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ -#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ -#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ +#define PHY_M_AN_NXT_PG BIT_15S /* Request Next Page */ +#define PHY_M_AN_ACK BIT_14S /* (ro) Acknowledge Received */ +#define PHY_M_AN_RF BIT_13S /* Remote Fault */ + /* Bit 12: reserved */ +#define PHY_M_AN_ASP BIT_11S /* Asymmetric Pause */ +#define PHY_M_AN_PC BIT_10S /* MAC Pause implemented */ +#define PHY_M_AN_100_T4 BIT_9S /* Not cap. 100Base-T4 (always 0) */ +#define PHY_M_AN_100_FD BIT_8S /* Advertise 100Base-TX Full Duplex */ +#define PHY_M_AN_100_HD BIT_7S /* Advertise 100Base-TX Half Duplex */ +#define PHY_M_AN_10_FD BIT_6S /* Advertise 10Base-TX Full Duplex */ +#define PHY_M_AN_10_HD BIT_5S /* Advertise 10Base-TX Half Duplex */ +#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ /* special defines for FIBER (88E1011S only) */ -#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ -#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ -#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ -#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ +#define PHY_M_AN_ASP_X BIT_8S /* Asymmetric Pause */ +#define PHY_M_AN_PC_X BIT_7S /* MAC Pause implemented */ +#define PHY_M_AN_1000X_AHD BIT_6S /* Advertise 10000Base-X Half Duplex */ +#define PHY_M_AN_1000X_AFD BIT_5S /* Advertise 10000Base-X Full Duplex */ /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ @@ -1111,102 +1120,144 @@ /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ -#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */ -#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */ -#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */ -#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ -#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ +#define PHY_M_1000C_MSE BIT_12S /* Manual Master/Slave Enable */ +#define PHY_M_1000C_MSC BIT_11S /* M/S Configuration (1=Master) */ +#define PHY_M_1000C_MPD BIT_10S /* Multi-Port Device */ +#define PHY_M_1000C_AFD BIT_9S /* Advertise Full Duplex */ +#define PHY_M_1000C_AHD BIT_8S /* Advertise Half Duplex */ /* Bit 7..0: reserved */ /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ -#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */ -#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */ +#define PHY_M_PC_ASS_CRS_TX BIT_11S /* Assert CRS on Transmit */ +#define PHY_M_PC_FL_GOOD BIT_10S /* Force Link Good */ #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ -#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */ +#define PHY_M_PC_ENA_EXT_D BIT_7S /* Enable Ext. Distance (10BT) */ #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ -#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */ -#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */ -#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */ -#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */ -#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */ +#define PHY_M_PC_DIS_125CLK BIT_4S /* Disable 125 CLK */ +#define PHY_M_PC_MAC_POW_UP BIT_3S /* MAC Power up */ +#define PHY_M_PC_SQE_T_ENA BIT_2S /* SQE Test Enabled */ +#define PHY_M_PC_POL_R_DIS BIT_1S /* Polarity Reversal Disabled */ +#define PHY_M_PC_DIS_JABBER BIT_0S /* Disable Jabber */ #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ -#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x) +#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) + #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +#define PHY_M_PC_ENA_DTE_DT BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */ +#define PHY_M_PC_ENA_ENE_DT BIT_14S /* Enable Energy Detect (sense & pulse) */ +#define PHY_M_PC_DIS_NLP_CK BIT_13S /* Disable Normal Link Puls (NLP) Check */ +#define PHY_M_PC_ENA_LIP_NP BIT_12S /* Enable Link Partner Next Page Reg. */ +#define PHY_M_PC_DIS_NLP_GN BIT_11S /* Disable Normal Link Puls Generation */ + +#define PHY_M_PC_DIS_SCRAMB BIT_9S /* Disable Scrambler */ +#define PHY_M_PC_DIS_FEFI BIT_8S /* Disable Far End Fault Indic. (FEFI) */ + +#define PHY_M_PC_SH_TP_SEL BIT_6S /* Shielded Twisted Pair Select */ +#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ + /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ -#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */ -#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */ +#define PHY_M_PS_SPEED_1000 BIT_15S /* 10 = 1000 Mbps */ +#define PHY_M_PS_SPEED_100 BIT_14S /* 01 = 100 Mbps */ #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ -#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */ -#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */ -#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */ -#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */ -#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */ -#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */ -#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */ -#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */ -#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */ -#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */ -#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */ -#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */ +#define PHY_M_PS_FULL_DUP BIT_13S /* Full Duplex */ +#define PHY_M_PS_PAGE_REC BIT_12S /* Page Received */ +#define PHY_M_PS_SPDUP_RES BIT_11S /* Speed & Duplex Resolved */ +#define PHY_M_PS_LINK_UP BIT_10S /* Link Up */ +#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ +#define PHY_M_PS_MDI_X_STAT BIT_6S /* MDI Crossover Stat (1=MDIX) */ +#define PHY_M_PS_DOWNS_STAT BIT_5S /* Downshift Status (1=downsh.) */ +#define PHY_M_PS_ENDET_STAT BIT_4S /* Energy Detect Status (1=act) */ +#define PHY_M_PS_TX_P_EN BIT_3S /* Tx Pause Enabled */ +#define PHY_M_PS_RX_P_EN BIT_2S /* Rx Pause Enabled */ +#define PHY_M_PS_POL_REV BIT_1S /* Polarity Reversed */ +#define PHY_M_PS_JABBER BIT_0S /* Jabber */ #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +#define PHY_M_PS_DTE_DETECT BIT_15S /* Data Terminal Equipment (DTE) Detected */ +#define PHY_M_PS_RES_SPEED BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ + /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ -#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */ -#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */ -#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */ -#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */ -#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */ -#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */ -#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */ -#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */ -#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */ -#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */ -#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */ -#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */ - /* Bit 3..2: reserved */ -#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */ -#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */ +#define PHY_M_IS_AN_ERROR BIT_15S /* Auto-Negotiation Error */ +#define PHY_M_IS_LSP_CHANGE BIT_14S /* Link Speed Changed */ +#define PHY_M_IS_DUP_CHANGE BIT_13S /* Duplex Mode Changed */ +#define PHY_M_IS_AN_PR BIT_12S /* Page Received */ +#define PHY_M_IS_AN_COMPL BIT_11S /* Auto-Negotiation Completed */ +#define PHY_M_IS_LST_CHANGE BIT_10S /* Link Status Changed */ +#define PHY_M_IS_SYMB_ERROR BIT_9S /* Symbol Error */ +#define PHY_M_IS_FALSE_CARR BIT_8S /* False Carrier */ +#define PHY_M_IS_FIFO_ERROR BIT_7S /* FIFO Overflow/Underrun Error */ +#define PHY_M_IS_MDI_CHANGE BIT_6S /* MDI Crossover Changed */ +#define PHY_M_IS_DOWNSH_DET BIT_5S /* Downshift Detected */ +#define PHY_M_IS_END_CHANGE BIT_4S /* Energy Detect Changed */ + /* Bit 3: reserved */ +#define PHY_M_IS_DTE_CHANGE BIT_2S /* DTE Power Det. Status Changed */ + /* (88E1111 only) */ +#define PHY_M_IS_POL_CHANGE BIT_1S /* Polarity Changed */ +#define PHY_M_IS_JABBER BIT_0S /* Jabber */ #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ -#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */ -#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */ +#define PHY_M_EC_ENA_BC_EXT BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */ +#define PHY_M_EC_ENA_LIN_LB BIT_14S /* Enable Line Loopback (88E1111 only) */ + /* Bit 13: reserved */ +#define PHY_M_EC_DIS_LINK_P BIT_12S /* Disable Link Pulses (88E1111 only) */ +#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ + /* (88E1011 only) */ +#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ + /* (88E1011 only) */ +#define PHY_M_EC_M_DSC_MSK2 (7<<9) /* Bit 11.. 9: Master Downshift Counter */ + /* (88E1111 only) */ +#define PHY_M_EC_DOWN_S_DIS BIT_8S /* Downshift Disable (88E1111 only) */ +#define PHY_M_EC_RX_TIM_CT BIT_7S /* RGMII Rx Timing Control*/ #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ -#define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */ +#define PHY_M_EC_FIB_AN_ENA BIT_3S /* Fiber Auto-Neg. Enable (88E1011S only) */ +#define PHY_M_EC_DTE_D_ENA BIT_2S /* DTE Detect Enable (88E1111 only) */ +#define PHY_M_EC_TX_TIM_CT BIT_1S /* RGMII Tx Timing Control */ +#define PHY_M_EC_TRANS_DIS BIT_0S /* Transmitter Disable (88E1111 only) */ #define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */ #define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */ #define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */ +#define PHY_M_EC_M_DSC_2(x) SHIFT9(x) /* 000=1x; 001=2x; 010=3x; 011=4x */ + /* 100=5x; 101=6x; 110=7x; 111=8x */ #define MAC_TX_CLK_0_MHZ 2 #define MAC_TX_CLK_2_5_MHZ 6 #define MAC_TX_CLK_25_MHZ 7 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ -#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */ +#define PHY_M_LEDC_DIS_LED BIT_15S /* Disable LED */ #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ -#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */ +#define PHY_M_LEDC_F_INT BIT_11S /* Force Interrupt */ #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ - /* Bit 7.. 5: reserved */ +#define PHY_M_LEDC_DP_C_LSB BIT_7S /* Duplex Control (LSB, 88E1111 only) */ +#define PHY_M_LEDC_TX_C_LSB BIT_6S /* Tx Control (LSB, 88E1111 only) */ +#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ + /* (88E1111 only) */ + /* Bit 7.. 5: reserved (88E1011 only) */ #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ -#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */ -#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */ -#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */ + /* (88E1011 only) */ +#define PHY_M_LEDC_DP_CTRL BIT_2S /* Duplex Control */ +#define PHY_M_LEDC_DP_C_MSB BIT_2S /* Duplex Control (MSB, 88E1111 only) */ +#define PHY_M_LEDC_RX_CTRL BIT_1S /* Rx Activity / Link */ +#define PHY_M_LEDC_TX_CTRL BIT_0S /* Tx Activity / Link */ +#define PHY_M_LEDC_TX_C_MSB BIT_0S /* Tx Control (MSB, 88E1111 only) */ -#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */ +#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) #define PULS_NO_STR 0 /* no pulse stretching */ #define PULS_21MS 1 /* 21 ms to 42 ms */ @@ -1217,7 +1268,7 @@ #define PULS_670MS 6 /* 670 ms to 1.3 s */ #define PULS_1300MS 7 /* 1.3 s to 2.7 s */ -#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */ +#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) #define BLINK_42MS 0 /* 42 ms */ #define BLINK_84MS 1 /* 84 ms */ @@ -1227,6 +1278,8 @@ /* values 5 - 7: reserved */ /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ +#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ + /* Bit 13..12: reserved */ #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ @@ -1240,30 +1293,35 @@ #define MO_LED_ON 3 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ - /* Bit 15.. 7: reserved */ -#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */ -#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */ -#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */ -#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */ + /* Bit 15.. 7: reserved */ +#define PHY_M_EC2_FI_IMPED BIT_6S /* Fiber Input Impedance */ +#define PHY_M_EC2_FO_IMPED BIT_5S /* Fiber Output Impedance */ +#define PHY_M_EC2_FO_M_CLK BIT_4S /* Fiber Mode Clock Enable */ +#define PHY_M_EC2_FO_BOOST BIT_3S /* Fiber Output Boost */ #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ -#define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */ -#define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */ -#define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */ -#define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */ -#define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */ -#define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */ - /* Bit 9..4: reserved */ -#define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */ -#define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */ - +#define PHY_M_FC_AUTO_SEL BIT_15S /* Fiber/Copper Auto Sel. Dis. */ +#define PHY_M_FC_AN_REG_ACC BIT_14S /* Fiber/Copper AN Reg. Access */ +#define PHY_M_FC_RESOLUTION BIT_13S /* Fiber/Copper Resolution */ +#define PHY_M_SER_IF_AN_BP BIT_12S /* Ser. IF AN Bypass Enable */ +#define PHY_M_SER_IF_BP_ST BIT_11S /* Ser. IF AN Bypass Status */ +#define PHY_M_IRQ_POLARITY BIT_10S /* IRQ polarity */ +#define PHY_M_DIS_AUT_MED BIT_9S /* Disable Aut. Medium Reg. Selection */ + /* (88E1111 only) */ + /* Bit 9.. 4: reserved (88E1011 only) */ +#define PHY_M_UNDOC1 BIT_7S /* undocumented bit !! */ +#define PHY_M_DTE_POW_STAT BIT_4S /* DTE Power Status (88E1111 only) */ +#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ -#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */ -#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */ - /* Bit 12.. 8: reserved */ -#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */ +#define PHY_M_CABD_ENA_TEST BIT_15S /* Enable Test (Page 0) */ +#define PHY_M_CABD_DIS_WAIT BIT_15S /* Disable Waiting Period (Page 1) */ + /* (88E1111 only) */ +#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ +#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ + /* (88E1111 only) */ +#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ #define CABD_STAT_NORMAL 0 @@ -1271,6 +1329,38 @@ #define CABD_STAT_OPEN 2 #define CABD_STAT_FAIL 3 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ + /* Bit 15..12: reserved (used internally) */ +#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ +#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ +#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ + +#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) +#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) +#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) + +#define LED_PAR_CTRL_COLX 0x00 +#define LED_PAR_CTRL_ERROR 0x01 +#define LED_PAR_CTRL_DUPLEX 0x02 +#define LED_PAR_CTRL_DP_COL 0x03 +#define LED_PAR_CTRL_SPEED 0x04 +#define LED_PAR_CTRL_LINK 0x05 +#define LED_PAR_CTRL_TX 0x06 +#define LED_PAR_CTRL_RX 0x07 +#define LED_PAR_CTRL_ACT 0x08 +#define LED_PAR_CTRL_LNK_RX 0x09 +#define LED_PAR_CTRL_LNK_AC 0x0a +#define LED_PAR_CTRL_ACT_BL 0x0b +#define LED_PAR_CTRL_TX_BL 0x0c +#define LED_PAR_CTRL_RX_BL 0x0d +#define LED_PAR_CTRL_COL_BL 0x0e +#define LED_PAR_CTRL_INACT 0x0f + +/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ +#define PHY_M_FESC_DIS_WAIT BIT_2S /* Disable TDR Waiting Period */ +#define PHY_M_FESC_ENA_MCLK BIT_1S /* Enable MAC Rx Clock in sleep mode */ +#define PHY_M_FESC_SEL_CL_A BIT_0S /* Select Class A driver (100B-TX) */ /* * GMAC registers @@ -1431,141 +1521,158 @@ */ /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ -#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */ -#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */ -#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */ -#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */ -#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */ -#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */ -#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */ -#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */ - /* Bit 7..6: reserved */ -#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */ -#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ -#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */ -#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */ -#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */ - /* Bit 0: reserved */ +#define GM_GPSR_SPEED BIT_15S /* Port Speed (1 = 100 Mbps) */ +#define GM_GPSR_DUPLEX BIT_14S /* Duplex Mode (1 = Full) */ +#define GM_GPSR_FC_TX_DIS BIT_13S /* Tx Flow-Control Mode Disabled */ +#define GM_GPSR_LINK_UP BIT_12S /* Link Up Status */ +#define GM_GPSR_PAUSE BIT_11S /* Pause State */ +#define GM_GPSR_TX_ACTIVE BIT_10S /* Tx in Progress */ +#define GM_GPSR_EXC_COL BIT_9S /* Excessive Collisions Occured */ +#define GM_GPSR_LAT_COL BIT_8S /* Late Collisions Occured */ + /* Bit 7.. 6: reserved */ +#define GM_GPSR_PHY_ST_CH BIT_5S /* PHY Status Change */ +#define GM_GPSR_GIG_SPEED BIT_4S /* Gigabit Speed (1 = 1000 Mbps) */ +#define GM_GPSR_PART_MODE BIT_3S /* Partition mode */ +#define GM_GPSR_FC_RX_DIS BIT_2S /* Rx Flow-Control Mode Disabled */ + /* Bit 2.. 0: reserved */ /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ - /* Bit 15: reserved */ -#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */ -#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */ -#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */ -#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */ -#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */ -#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */ -#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */ -#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */ -#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */ -#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */ -#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */ -#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */ -#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */ -#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */ -#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */ +#define GM_GPCR_RMII_PH_ENA BIT_15S /* Enable RMII for PHY (Yukon-FE only) */ +#define GM_GPCR_RMII_LB_ENA BIT_14S /* Enable RMII Loopback (Yukon-FE only) */ +#define GM_GPCR_FC_TX_DIS BIT_13S /* Disable Tx Flow-Control Mode */ +#define GM_GPCR_TX_ENA BIT_12S /* Enable Transmit */ +#define GM_GPCR_RX_ENA BIT_11S /* Enable Receive */ + /* Bit 10: reserved */ +#define GM_GPCR_LOOP_ENA BIT_9S /* Enable MAC Loopback Mode */ +#define GM_GPCR_PART_ENA BIT_8S /* Enable Partition Mode */ +#define GM_GPCR_GIGS_ENA BIT_7S /* Gigabit Speed (1000 Mbps) */ +#define GM_GPCR_FL_PASS BIT_6S /* Force Link Pass */ +#define GM_GPCR_DUP_FULL BIT_5S /* Full Duplex Mode */ +#define GM_GPCR_FC_RX_DIS BIT_4S /* Disable Rx Flow-Control Mode */ +#define GM_GPCR_SPEED_100 BIT_3S /* Port Speed 100 Mbps */ +#define GM_GPCR_AU_DUP_DIS BIT_2S /* Disable Auto-Update Duplex */ +#define GM_GPCR_AU_FCT_DIS BIT_1S /* Disable Auto-Update Flow-C. */ +#define GM_GPCR_AU_SPD_DIS BIT_0S /* Disable Auto-Update Speed */ #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ GM_GPCR_AU_SPD_DIS) /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ -#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */ -#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */ -#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */ -#define GM_TXCR_COL_THR_MSK (1<<10) /* Bit 12..10: Collision Threshold */ +#define GM_TXCR_FORCE_JAM BIT_15S /* Force Jam / Flow-Control */ +#define GM_TXCR_CRC_DIS BIT_14S /* Disable insertion of CRC */ +#define GM_TXCR_PAD_DIS BIT_13S /* Disable padding of packets */ +#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ + /* Bit 9.. 8: reserved */ +#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ + /* (Yukon-2 only) */ #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) #define TX_COL_DEF 0x04 /* GM_RX_CTRL 16 bit r/w Receive Control Register */ -#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */ -#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */ -#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */ -#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */ +#define GM_RXCR_UCF_ENA BIT_15S /* Enable Unicast filtering */ +#define GM_RXCR_MCF_ENA BIT_14S /* Enable Multicast filtering */ +#define GM_RXCR_CRC_DIS BIT_13S /* Remove 4-byte CRC */ +#define GM_RXCR_PASS_FC BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */ + /* Bit 11.. 0: reserved */ /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ -#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */ -#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */ -#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */ - /* Bit 3..0: reserved */ +#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length */ +#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG */ +#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data */ +#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ + /* (Yukon-2 only) */ #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) #define TX_JAM_LEN_DEF 0x03 #define TX_JAM_IPG_DEF 0x0b #define TX_IPG_JAM_DEF 0x1c +#define TX_BOF_LIM_DEF 0x04 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ -#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */ -#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */ -#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */ -#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */ - /* Bit 7..5: reserved */ -#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ +#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ + /* r/o on Yukon, r/w on Yukon-EC */ +#define GM_SMOD_LIMIT_4 BIT_10S /* 4 consecutive Tx trials */ +#define GM_SMOD_VLAN_ENA BIT_9S /* Enable VLAN (Max. Frame Len) */ +#define GM_SMOD_JUMBO_ENA BIT_8S /* Enable Jumbo (Max. Frame Len) */ + /* Bit 7.. 5: reserved */ +#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) -#define DATA_BLIND_DEF 0x04 +#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) -#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) +#define DATA_BLIND_DEF 0x04 #define IPG_DATA_DEF 0x1e /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ -#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/ -#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */ -#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */ - /* Bit 2..0: reserved */ +#define GM_SMI_CT_OP_RD BIT_5S /* OpCode Read (0=Write)*/ +#define GM_SMI_CT_RD_VAL BIT_4S /* Read Valid (Read completed) */ +#define GM_SMI_CT_BUSY BIT_3S /* Busy (Operation in progress) */ + /* Bit 2.. 0: reserved */ #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ - /* Bit 15..6: reserved */ -#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */ -#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */ - /* Bit 3..0: reserved */ + /* Bit 15.. 6: reserved */ +#define GM_PAR_MIB_CLR BIT_5S /* Set MIB Clear Counter Mode */ +#define GM_PAR_MIB_TST BIT_4S /* MIB Load Counter (Test Mode) */ + /* Bit 3.. 0: reserved */ /* Receive Frame Status Encoding */ -#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ +#define GMR_FS_LEN_MSK (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ /* Bit 15..14: reserved */ -#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */ -#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */ -#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */ -#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */ -#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */ -#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */ -#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */ -#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */ -#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */ -#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */ -#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */ +#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ +#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ +#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ +#define GMR_FS_MC BIT_10 /* Multicast Packet */ +#define GMR_FS_BC BIT_9 /* Broadcast Packet */ +#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ +#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ +#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ +#define GMR_FS_MII_ERR BIT_5 /* MII Error */ +#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ +#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ /* Bit 2: reserved */ -#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */ -#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */ +#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ +#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ + +#define GMR_FS_LEN_SHIFT 16 /* * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) */ -#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \ - GMR_FS_LONG_ERR | \ +#ifdef SK_DIAG +#define GMR_FS_ANY_ERR ( \ + GMR_FS_RX_FF_OV | \ + GMR_FS_CRC_ERR | \ GMR_FS_MII_ERR | \ GMR_FS_BAD_FC | \ GMR_FS_GOOD_FC | \ GMR_FS_JABBER) - -/* Rx GMAC FIFO Flush Mask (default) */ -#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \ +#else +#define GMR_FS_ANY_ERR ( \ GMR_FS_RX_FF_OV | \ + GMR_FS_CRC_ERR | \ + GMR_FS_FRAGMENT | \ + GMR_FS_LONG_ERR | \ GMR_FS_MII_ERR | \ GMR_FS_BAD_FC | \ GMR_FS_GOOD_FC | \ GMR_FS_UN_SIZE | \ GMR_FS_JABBER) +#endif + +/* Rx GMAC FIFO Flush Mask (default) */ +#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR /* typedefs *******************************************************************/ diff -ruN linux/drivers/net/sk98lin/skaddr.c linux-new/drivers/net/sk98lin/skaddr.c --- linux/drivers/net/sk98lin/skaddr.c 2004-09-07 13:32:31.461547659 +0200 +++ linux-new/drivers/net/sk98lin/skaddr.c 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skaddr.c * Project: Gigabit Ethernet Adapters, ADDR-Module - * Version: $Revision: 1.52 $ - * Date: $Date: 2003/06/02 13:46:15 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2003/11/24 12:22:01 $ * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode. * ******************************************************************************/ @@ -44,7 +44,7 @@ #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "@(#) $Id: skaddr.c,v 1.52 2003/06/02 13:46:15 tschilli Exp $ (C) Marvell."; + "@(#) $Id: skaddr.c,v 2.2 2003/11/24 12:22:01 mkarl Exp $ (C) Marvell."; #endif /* DEBUG ||!LINT || !SK_SLIM */ #define __SKADDR_C @@ -213,7 +213,7 @@ pAC->Addr.Net[i].PermanentMacAddress.a[2], pAC->Addr.Net[i].PermanentMacAddress.a[3], pAC->Addr.Net[i].PermanentMacAddress.a[4], - pAC->Addr.Net[i].PermanentMacAddress.a[5])) + pAC->Addr.Net[i].PermanentMacAddress.a[5])); SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n", @@ -223,7 +223,7 @@ pAC->Addr.Net[i].CurrentMacAddress.a[2], pAC->Addr.Net[i].CurrentMacAddress.a[3], pAC->Addr.Net[i].CurrentMacAddress.a[4], - pAC->Addr.Net[i].CurrentMacAddress.a[5])) + pAC->Addr.Net[i].CurrentMacAddress.a[5])); } #endif /* DEBUG */ @@ -266,7 +266,7 @@ pAPort->PermanentMacAddress.a[2], pAPort->PermanentMacAddress.a[3], pAPort->PermanentMacAddress.a[4], - pAPort->PermanentMacAddress.a[5])) + pAPort->PermanentMacAddress.a[5])); SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -275,7 +275,7 @@ pAPort->CurrentMacAddress.a[2], pAPort->CurrentMacAddress.a[3], pAPort->CurrentMacAddress.a[4], - pAPort->CurrentMacAddress.a[5])) + pAPort->CurrentMacAddress.a[5])); #endif /* DEBUG */ } /* pAC->Addr.InitDone = SK_INIT_IO; */ @@ -339,10 +339,14 @@ } if (pAC->GIni.GIGenesis) { +#ifdef GENESIS ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags); +#endif } else { +#ifdef YUKON ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags); +#endif } return (ReturnCode); @@ -352,7 +356,7 @@ #endif /* !SK_SLIM */ #ifndef SK_SLIM - +#ifdef GENESIS /****************************************************************************** * * SkAddrXmacMcClear - clear the multicast table @@ -404,11 +408,11 @@ return (SK_ADDR_SUCCESS); } /* SkAddrXmacMcClear */ - +#endif /* GENESIS */ #endif /* !SK_SLIM */ #ifndef SK_SLIM - +#ifdef YUKON /****************************************************************************** * * SkAddrGmacMcClear - clear the multicast table @@ -447,7 +451,7 @@ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])); #endif /* DEBUG */ /* Clear InexactFilter */ @@ -489,7 +493,7 @@ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])); #endif /* DEBUG */ if (!(Flags & SK_MC_SW_ONLY)) { @@ -499,9 +503,10 @@ return (SK_ADDR_SUCCESS); } /* SkAddrGmacMcClear */ +#endif /* YUKON */ #ifndef SK_ADDR_CHEAT - +#ifdef GENESIS /****************************************************************************** * * SkXmacMcHash - hash multicast address @@ -538,8 +543,9 @@ return (Crc & ((1 << HASH_BITS) - 1)); } /* SkXmacMcHash */ +#endif /* GENESIS */ - +#ifdef YUKON /****************************************************************************** * * SkGmacMcHash - hash multicast address @@ -597,7 +603,7 @@ return (Crc & ((1 << HASH_BITS) - 1)); } /* SkGmacMcHash */ - +#endif /* YUKON */ #endif /* !SK_ADDR_CHEAT */ /****************************************************************************** @@ -638,17 +644,21 @@ } if (pAC->GIni.GIGenesis) { +#ifdef GENESIS ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); +#endif } else { +#ifdef YUKON ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); +#endif } return (ReturnCode); } /* SkAddrMcAdd */ - +#ifdef GENESIS /****************************************************************************** * * SkAddrXmacMcAdd - add a multicast address to a port @@ -758,8 +768,9 @@ } } /* SkAddrXmacMcAdd */ +#endif /* GENESIS */ - +#ifdef YUKON /****************************************************************************** * * SkAddrGmacMcAdd - add a multicast address to a port @@ -821,7 +832,7 @@ pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7])); #endif /* DEBUG */ } else { /* not permanent => DRV */ @@ -845,7 +856,7 @@ pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7])); #endif /* DEBUG */ } @@ -860,7 +871,7 @@ return (SK_MC_FILTERING_INEXACT); } /* SkAddrGmacMcAdd */ - +#endif /* YUKON */ #endif /* !SK_SLIM */ /****************************************************************************** @@ -948,13 +959,13 @@ SK_ADDR_PORT *pAPort; SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber)) + ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber)); pAPort = &pAC->Addr.Port[PortNumber]; #ifdef DEBUG SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])); #endif /* DEBUG */ /* Start with 0 to also program the logical MAC address. */ @@ -1043,7 +1054,7 @@ pAPort->Exact[i].a[2], pAPort->Exact[i].a[3], pAPort->Exact[i].a[4], - pAPort->Exact[i].a[5])) + pAPort->Exact[i].a[5])); } #endif /* DEBUG */ @@ -1095,13 +1106,13 @@ SK_ADDR_PORT *pAPort; SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber)) + ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber)); pAPort = &pAC->Addr.Port[PortNumber]; #ifdef DEBUG SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])); #endif /* DEBUG */ #ifndef SK_SLIM @@ -1157,7 +1168,7 @@ pAPort->Exact[0].a[2], pAPort->Exact[0].a[3], pAPort->Exact[0].a[4], - pAPort->Exact[0].a[5])) + pAPort->Exact[0].a[5])); SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -1166,7 +1177,7 @@ pAPort->CurrentMacAddress.a[2], pAPort->CurrentMacAddress.a[3], pAPort->CurrentMacAddress.a[4], - pAPort->CurrentMacAddress.a[5])) + pAPort->CurrentMacAddress.a[5])); #endif /* DEBUG */ #ifndef SK_SLIM @@ -1373,7 +1384,7 @@ pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2], pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3], pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4], - pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5])) + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5])); SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -1382,7 +1393,7 @@ pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2], pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3], pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4], - pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5])) + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5])); #endif /* DEBUG */ /* Write address to first exact match entry of active port. */ diff -ruN linux/drivers/net/sk98lin/skcsum.c linux-new/drivers/net/sk98lin/skcsum.c --- linux/drivers/net/sk98lin/skcsum.c 2004-08-14 12:54:47.000000000 +0200 +++ linux-new/drivers/net/sk98lin/skcsum.c 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skcsum.c * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.12 $ - * Date: $Date: 2003/08/20 13:55:53 $ + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:08 $ * Purpose: Store/verify Internet checksum in send/receive packets. * ******************************************************************************/ @@ -25,7 +25,7 @@ #ifndef lint static const char SysKonnectFileId[] = - "@(#) $Id: skcsum.c,v 1.12 2003/08/20 13:55:53 mschmid Exp $ (C) SysKonnect."; + "@(#) $Id: skcsum.c,v 2.1 2003/10/27 14:16:08 amock Exp $ (C) SysKonnect."; #endif /* !lint */ /****************************************************************************** diff -ruN linux/drivers/net/sk98lin/skdim.c linux-new/drivers/net/sk98lin/skdim.c --- linux/drivers/net/sk98lin/skdim.c 2004-08-14 12:55:09.000000000 +0200 +++ linux-new/drivers/net/sk98lin/skdim.c 2004-08-26 10:28:00.000000000 +0200 @@ -1,18 +1,29 @@ /****************************************************************************** * - * Name: skdim.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.5 $ - * Date: $Date: 2003/11/28 12:55:40 $ - * Purpose: All functions to maintain interrupt moderation + * Name: skdim.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.5 $ + * Date: $Date: 2004/07/17 13:28:43 $ + * Purpose: All functions regardig interrupt moderation * ******************************************************************************/ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect GmbH. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet + * Server Adapters. + * + * Author: Ralph Roesler (rroesler@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * The technical manual for the adapters is available from SysKonnect's + * web pages: www.syskonnect.com + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -20,723 +31,367 @@ * * The information in this file is provided "AS IS" without warranty. * - ******************************************************************************/ + *****************************************************************************/ -/****************************************************************************** - * - * Description: - * - * This module is intended to manage the dynamic interrupt moderation on both - * GEnesis and Yukon adapters. - * - * Include File Hierarchy: - * - * "skdrv1st.h" - * "skdrv2nd.h" - * - ******************************************************************************/ - -#ifndef lint -static const char SysKonnectFileId[] = - "@(#) $Id: skdim.c,v 1.5 2003/11/28 12:55:40 rroesler Exp $ (C) SysKonnect."; -#endif - -#define __SKADDR_C - -#ifdef __cplusplus -#error C++ is not yet supported. -extern "C" { -#endif - -/******************************************************************************* -** -** Includes -** -*******************************************************************************/ - -#ifndef __INC_SKDRV1ST_H #include "h/skdrv1st.h" -#endif - -#ifndef __INC_SKDRV2ND_H #include "h/skdrv2nd.h" -#endif -#include - -/******************************************************************************* -** -** Defines -** -*******************************************************************************/ - -/******************************************************************************* -** -** Typedefs -** -*******************************************************************************/ +/****************************************************************************** + * + * Local Function Prototypes + * + *****************************************************************************/ -/******************************************************************************* -** -** Local function prototypes -** -*******************************************************************************/ - -static unsigned int GetCurrentSystemLoad(SK_AC *pAC); -static SK_U64 GetIsrCalls(SK_AC *pAC); -static SK_BOOL IsIntModEnabled(SK_AC *pAC); -static void SetCurrIntCtr(SK_AC *pAC); -static void EnableIntMod(SK_AC *pAC); -static void DisableIntMod(SK_AC *pAC); -static void ResizeDimTimerDuration(SK_AC *pAC); -static void DisplaySelectedModerationType(SK_AC *pAC); -static void DisplaySelectedModerationMask(SK_AC *pAC); -static void DisplayDescrRatio(SK_AC *pAC); +static SK_U64 getIsrCalls(SK_AC *pAC); +static SK_BOOL isIntModEnabled(SK_AC *pAC); +static void setCurrIntCtr(SK_AC *pAC); +static void enableIntMod(SK_AC *pAC); +static void disableIntMod(SK_AC *pAC); -/******************************************************************************* -** -** Global variables -** -*******************************************************************************/ +#define M_DIMINFO pAC->DynIrqModInfo -/******************************************************************************* -** -** Local variables -** -*******************************************************************************/ +/****************************************************************************** + * + * Global Functions + * + *****************************************************************************/ -/******************************************************************************* -** -** Global functions -** -*******************************************************************************/ +/***************************************************************************** + * + * SkDimModerate - Moderates the IRQs depending on the current needs + * + * Description: + * Moderation of IRQs depends on the number of occurred IRQs with + * respect to the previous moderation cycle. + * + * Returns: N/A + * + */ +void SkDimModerate( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_U64 IsrCalls = getIsrCalls(pAC); + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n")); + + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + if (isIntModEnabled(pAC)) { + if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) { + disableIntMod(pAC); + } + } else { + if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) { + enableIntMod(pAC); + } + } + } + setCurrIntCtr(pAC); -/******************************************************************************* -** Function : SkDimModerate -** Description : Called in every ISR to check if moderation is to be applied -** or not for the current number of interrupts -** Programmer : Ralph Roesler -** Last Modified: 22-mar-03 -** Returns : void (!) -** Notes : - -*******************************************************************************/ - -void -SkDimModerate(SK_AC *pAC) { - unsigned int CurrSysLoad = 0; /* expressed in percent */ - unsigned int LoadIncrease = 0; /* expressed in percent */ - SK_U64 ThresholdInts = 0; - SK_U64 IsrCallsPerSec = 0; + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n")); +} -#define M_DIMINFO pAC->DynIrqModInfo +/***************************************************************************** + * + * SkDimStartModerationTimer - Starts the moderation timer + * + * Description: + * Dynamic interrupt moderation is regularly checked using the + * so-called moderation timer. This timer is started with this function. + * + * Returns: N/A + */ +void SkDimStartModerationTimer( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_EVPARA EventParam; /* Event struct for timer event */ + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==> SkDimStartModerationTimer\n")); - if (!IsIntModEnabled(pAC)) { - if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { - CurrSysLoad = GetCurrentSystemLoad(pAC); - if (CurrSysLoad > 75) { - /* - ** More than 75% total system load! Enable the moderation - ** to shield the system against too many interrupts. - */ - EnableIntMod(pAC); - } else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) { - LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad); - if (LoadIncrease > ((M_DIMINFO.PrevSysLoad * - C_INT_MOD_ENABLE_PERCENTAGE) / 100)) { - if (CurrSysLoad > 10) { - /* - ** More than 50% increase with respect to the - ** previous load of the system. Most likely this - ** is due to our ISR-proc... - */ - EnableIntMod(pAC); - } - } - } else { - /* - ** Neither too much system load at all nor too much increase - ** with respect to the previous system load. Hence, we can leave - ** the ISR-handling like it is without enabling moderation. - */ - } - M_DIMINFO.PrevSysLoad = CurrSysLoad; - } - } else { - if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { - ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec * - C_INT_MOD_DISABLE_PERCENTAGE) / 100); - IsrCallsPerSec = GetIsrCalls(pAC); - if (IsrCallsPerSec <= ThresholdInts) { - /* - ** The number of interrupts within the last second is - ** lower than the disable_percentage of the desried - ** maxrate. Therefore we can disable the moderation. - */ - DisableIntMod(pAC); - M_DIMINFO.MaxModIntsPerSec = - (M_DIMINFO.MaxModIntsPerSecUpperLimit + - M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2; - } else { - /* - ** The number of interrupts per sec is the same as expected. - ** Evalulate the descriptor-ratio. If it has changed, a resize - ** in the moderation timer might be usefull - */ - if (M_DIMINFO.AutoSizing) { - ResizeDimTimerDuration(pAC); - } - } - } - } - - /* - ** Some information to the log... - */ - if (M_DIMINFO.DisplayStats) { - DisplaySelectedModerationType(pAC); - DisplaySelectedModerationMask(pAC); - DisplayDescrRatio(pAC); - } + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = SK_DRV_MODERATION_TIMER; + SkTimerStart(pAC, pAC->IoBase, + &pAC->DynIrqModInfo.ModTimer, + pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000, + SKGE_DRV, SK_DRV_TIMER, EventParam); + } - M_DIMINFO.NbrProcessedDescr = 0; - SetCurrIntCtr(pAC); + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== SkDimStartModerationTimer\n")); } -/******************************************************************************* -** Function : SkDimStartModerationTimer -** Description : Starts the audit-timer for the dynamic interrupt moderation -** Programmer : Ralph Roesler -** Last Modified: 22-mar-03 -** Returns : void (!) -** Notes : - -*******************************************************************************/ - -void -SkDimStartModerationTimer(SK_AC *pAC) { - SK_EVPARA EventParam; /* Event struct for timer event */ - - SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); - EventParam.Para32[0] = SK_DRV_MODERATION_TIMER; - SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer, - SK_DRV_MODERATION_TIMER_LENGTH, - SKGE_DRV, SK_DRV_TIMER, EventParam); -} +/***************************************************************************** + * + * SkDimEnableModerationIfNeeded - Enables or disables any moderationtype + * + * Description: + * This function effectively initializes the IRQ moderation of a network + * adapter. Depending on the configuration, this might be either static + * or dynamic. If no moderation is configured, this function will do + * nothing. + * + * Returns: N/A + */ +void SkDimEnableModerationIfNeeded( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==> SkDimEnableModerationIfNeeded\n")); + + if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) { + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) { + enableIntMod(pAC); + } else { /* must be C_INT_MOD_DYNAMIC */ + SkDimStartModerationTimer(pAC); + } + } -/******************************************************************************* -** Function : SkDimEnableModerationIfNeeded -** Description : Either enables or disables moderation -** Programmer : Ralph Roesler -** Last Modified: 22-mar-03 -** Returns : void (!) -** Notes : This function is called when a particular adapter is opened -** There is no Disable function, because when all interrupts -** might be disable, the moderation timer has no meaning at all -******************************************************************************/ - -void -SkDimEnableModerationIfNeeded(SK_AC *pAC) { - - if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) { - EnableIntMod(pAC); /* notification print in this function */ - } else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { - SkDimStartModerationTimer(pAC); - if (M_DIMINFO.DisplayStats) { - printk("Dynamic moderation has been enabled\n"); - } - } else { - if (M_DIMINFO.DisplayStats) { - printk("No moderation has been enabled\n"); - } - } + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== SkDimEnableModerationIfNeeded\n")); } -/******************************************************************************* -** Function : SkDimDisplayModerationSettings -** Description : Displays the current settings regaring interrupt moderation -** Programmer : Ralph Roesler -** Last Modified: 22-mar-03 -** Returns : void (!) -** Notes : - -*******************************************************************************/ - -void -SkDimDisplayModerationSettings(SK_AC *pAC) { - DisplaySelectedModerationType(pAC); - DisplaySelectedModerationMask(pAC); -} +/***************************************************************************** + * + * SkDimDisableModeration - disables moderation if it is enabled + * + * Description: + * Disabling of the moderation requires that is enabled already. + * + * Returns: N/A + */ +void SkDimDisableModeration( +SK_AC *pAC, /* pointer to adapter control context */ +int CurrentModeration) /* type of current moderation */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==> SkDimDisableModeration\n")); + + if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) { + if (CurrentModeration == C_INT_MOD_STATIC) { + disableIntMod(pAC); + } else { /* must be C_INT_MOD_DYNAMIC */ + SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer); + disableIntMod(pAC); + } + } -/******************************************************************************* -** -** Local functions -** -*******************************************************************************/ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== SkDimDisableModeration\n")); +} -/******************************************************************************* -** Function : GetCurrentSystemLoad -** Description : Retrieves the current system load of the system. This load -** is evaluated for all processors within the system. -** Programmer : Ralph Roesler -** Last Modified: 22-mar-03 -** Returns : unsigned int: load expressed in percentage -** Notes : The possible range being returned is from 0 up to 100. -** Whereas 0 means 'no load at all' and 100 'system fully loaded' -** It is impossible to determine what actually causes the system -** to be in 100%, but maybe that is due to too much interrupts. -*******************************************************************************/ - -static unsigned int -GetCurrentSystemLoad(SK_AC *pAC) { - unsigned long jif = jiffies; - unsigned int UserTime = 0; - unsigned int SystemTime = 0; - unsigned int NiceTime = 0; - unsigned int IdleTime = 0; - unsigned int TotalTime = 0; - unsigned int UsedTime = 0; - unsigned int SystemLoad = 0; +/****************************************************************************** + * + * Local Functions + * + *****************************************************************************/ - /* unsigned int NbrCpu = 0; */ +/***************************************************************************** + * + * getIsrCalls - evaluate the number of IRQs handled in mod interval + * + * Description: + * Depending on the selected moderation mask, this function will return + * the number of interrupts handled in the previous moderation interval. + * This evaluated number is based on the current number of interrupts + * stored in PNMI-context and the previous stored interrupts. + * + * Returns: + * the number of IRQs handled + */ +static SK_U64 getIsrCalls( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_U64 RxPort0IntDiff = 0, RxPort1IntDiff = 0; + SK_U64 TxPort0IntDiff = 0, TxPort1IntDiff = 0; + SK_U64 StatusPort0IntDiff = 0, StatusPort1IntDiff = 0; + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n")); + + if (!CHIP_ID_YUKON_2(pAC)) { + if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) || + (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) { + if (pAC->GIni.GIMacsFound == 2) { + TxPort1IntDiff = + pAC->Pnmi.Port[1].TxIntrCts - + M_DIMINFO.PrevPort1TxIntrCts; + } + TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts - + M_DIMINFO.PrevPort0TxIntrCts; + } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) || + (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) { + if (pAC->GIni.GIMacsFound == 2) { + RxPort1IntDiff = + pAC->Pnmi.Port[1].RxIntrCts - + M_DIMINFO.PrevPort1RxIntrCts; + } + RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - + M_DIMINFO.PrevPort0RxIntrCts; + } else { + if (pAC->GIni.GIMacsFound == 2) { + RxPort1IntDiff = + pAC->Pnmi.Port[1].RxIntrCts - + M_DIMINFO.PrevPort1RxIntrCts; + TxPort1IntDiff = + pAC->Pnmi.Port[1].TxIntrCts - + M_DIMINFO.PrevPort1TxIntrCts; + } + RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - + M_DIMINFO.PrevPort0RxIntrCts; + TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts - + M_DIMINFO.PrevPort0TxIntrCts; + } + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n")); + return (RxPort0IntDiff + RxPort1IntDiff + + TxPort0IntDiff + TxPort1IntDiff); + } /* - ** The following lines have been commented out, because - ** from kernel 2.5.44 onwards, the kernel-owned structure - ** - ** struct kernel_stat kstat - ** - ** is not marked as an exported symbol in the file + ** We have a Yukon2 compliant chipset if we come up to here ** - ** kernel/ksyms.c - ** - ** As a consequence, using this driver as KLM is not possible - ** and any access of the structure kernel_stat via the - ** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided. - ** - ** The kstat-information might be added again in future - ** versions of the 2.5.xx kernel, but for the time being, - ** number of interrupts will serve as indication how much - ** load we currently have... - ** - ** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) { - ** UserTime = UserTime + kstat_cpu(NbrCpu).cpustat.user; - ** NiceTime = NiceTime + kstat_cpu(NbrCpu).cpustat.nice; - ** SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system; - ** } + if (pAC->GIni.GIMacsFound == 2) { + StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts - + M_DIMINFO.PrevPort1StatusIntrCts; + } + StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts - + M_DIMINFO.PrevPort0StatusIntrCts; */ - SK_U64 ThresholdInts = 0; - SK_U64 IsrCallsPerSec = 0; - - ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec * - C_INT_MOD_ENABLE_PERCENTAGE) + 100); - IsrCallsPerSec = GetIsrCalls(pAC); - if (IsrCallsPerSec >= ThresholdInts) { - /* - ** We do not know how much the real CPU-load is! - ** Return 80% as a default in order to activate DIM - */ - SystemLoad = 80; - return (SystemLoad); - } - - UsedTime = UserTime + NiceTime + SystemTime; - - IdleTime = jif * num_online_cpus() - UsedTime; - TotalTime = UsedTime + IdleTime; - - SystemLoad = ( 100 * (UsedTime - M_DIMINFO.PrevUsedTime) ) / - (TotalTime - M_DIMINFO.PrevTotalTime); + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==>getIsrCalls (CHIP_ID_YUKON_2)\n")); + return (StatusPort0IntDiff + StatusPort1IntDiff); +} - if (M_DIMINFO.DisplayStats) { - printk("Current system load is: %u\n", SystemLoad); +/***************************************************************************** + * + * setCurrIntCtr - stores the current number of interrupts + * + * Description: + * Stores the current number of occurred interrupts in the adapter + * context. This is needed to evaluate the umber of interrupts within + * the moderation interval. + * + * Returns: N/A + * + */ +static void setCurrIntCtr( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n")); + + if (!CHIP_ID_YUKON_2(pAC)) { + if (pAC->GIni.GIMacsFound == 2) { + M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts; + M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts; + } + M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts; + M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts; + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n")); + return; } - M_DIMINFO.PrevTotalTime = TotalTime; - M_DIMINFO.PrevUsedTime = UsedTime; - - return (SystemLoad); + /* + ** We have a Yukon2 compliant chipset if we come up to here + ** + if (pAC->GIni.GIMacsFound == 2) { + M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts; + } + M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts; + */ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n")); } -/******************************************************************************* -** Function : GetIsrCalls -** Description : Depending on the selected moderation mask, this function will -** return the number of interrupts handled in the previous time- -** frame. This evaluated number is based on the current number -** of interrupts stored in PNMI-context and the previous stored -** interrupts. -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : int: the number of interrupts being executed in the last -** timeframe -** Notes : It makes only sense to call this function, when dynamic -** interrupt moderation is applied -*******************************************************************************/ - -static SK_U64 -GetIsrCalls(SK_AC *pAC) { - SK_U64 RxPort0IntDiff = 0; - SK_U64 RxPort1IntDiff = 0; - SK_U64 TxPort0IntDiff = 0; - SK_U64 TxPort1IntDiff = 0; - - if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) { - if (pAC->GIni.GIMacsFound == 2) { - TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts - - pAC->DynIrqModInfo.PrevPort1TxIntrCts; - } - TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts - - pAC->DynIrqModInfo.PrevPort0TxIntrCts; - } else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) { - if (pAC->GIni.GIMacsFound == 2) { - RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts - - pAC->DynIrqModInfo.PrevPort1RxIntrCts; - } - RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - - pAC->DynIrqModInfo.PrevPort0RxIntrCts; - } else { - if (pAC->GIni.GIMacsFound == 2) { - RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts - - pAC->DynIrqModInfo.PrevPort1RxIntrCts; - TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts - - pAC->DynIrqModInfo.PrevPort1TxIntrCts; - } - RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - - pAC->DynIrqModInfo.PrevPort0RxIntrCts; - TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts - - pAC->DynIrqModInfo.PrevPort0TxIntrCts; - } - - return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff); +/***************************************************************************** + * + * isIntModEnabled - returns the current state of interrupt moderation + * + * Description: + * This function retrieves the current value of the interrupt moderation + * command register. Its content determines whether any moderation is + * running or not. + * + * Returns: + * SK_TRUE : IRQ moderation is currently active + * SK_FALSE: No IRQ moderation is active + */ +static SK_BOOL isIntModEnabled( +SK_AC *pAC) /* pointer to adapter control context */ +{ + unsigned long CtrCmd; + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n")); + + SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd); + if ((CtrCmd & TIM_START) == TIM_START) { + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== isIntModEnabled (SK_TRUE)\n")); + return SK_TRUE; + } + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== isIntModEnabled (SK_FALSE)\n")); + return SK_FALSE; } -/******************************************************************************* -** Function : GetRxCalls -** Description : This function will return the number of times a receive inter- -** rupt was processed. This is needed to evaluate any resizing -** factor. -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : SK_U64: the number of RX-ints being processed -** Notes : It makes only sense to call this function, when dynamic -** interrupt moderation is applied -*******************************************************************************/ - -static SK_U64 -GetRxCalls(SK_AC *pAC) { - SK_U64 RxPort0IntDiff = 0; - SK_U64 RxPort1IntDiff = 0; - - if (pAC->GIni.GIMacsFound == 2) { - RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts - - pAC->DynIrqModInfo.PrevPort1RxIntrCts; - } - RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - - pAC->DynIrqModInfo.PrevPort0RxIntrCts; - - return (RxPort0IntDiff + RxPort1IntDiff); -} +/***************************************************************************** + * + * enableIntMod - enables the interrupt moderation + * + * Description: + * Enabling the interrupt moderation is done by putting the desired + * moderation interval in the B2_IRQM_INI register, specifying the + * desired maks in the B2_IRQM_MSK register and finally starting the + * IRQ moderation timer using the B2_IRQM_CTRL register. + * + * Returns: N/A + * + */ +static void enableIntMod( +SK_AC *pAC) /* pointer to adapter control context */ +{ + unsigned long ModBase; + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n")); + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec; + } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) { + ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec; + } else { + ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec; + } -/******************************************************************************* -** Function : SetCurrIntCtr -** Description : Will store the current number orf occured interrupts in the -** adapter context. This is needed to evaluated the number of -** interrupts within a current timeframe. -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : void (!) -** Notes : - -*******************************************************************************/ - -static void -SetCurrIntCtr(SK_AC *pAC) { - if (pAC->GIni.GIMacsFound == 2) { - pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts; - pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts; - } - pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts; - pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts; -} + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration); + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); -/******************************************************************************* -** Function : IsIntModEnabled() -** Description : Retrieves the current value of the interrupts moderation -** command register. Its content determines whether any -** moderation is running or not. -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : SK_TRUE : if mod timer running -** SK_FALSE : if no moderation is being performed -** Notes : - -*******************************************************************************/ - -static SK_BOOL -IsIntModEnabled(SK_AC *pAC) { - unsigned long CtrCmd; - - SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd); - if ((CtrCmd & TIM_START) == TIM_START) { - return SK_TRUE; - } else { - return SK_FALSE; - } + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n")); } -/******************************************************************************* -** Function : EnableIntMod() -** Description : Enables the interrupt moderation using the values stored in -** in the pAC->DynIntMod data structure -** Programmer : Ralph Roesler -** Last Modified: 22-mar-03 -** Returns : - -** Notes : - -*******************************************************************************/ - -static void -EnableIntMod(SK_AC *pAC) { - unsigned long ModBase; - - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { - ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec; - } else { - ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec; - } - - SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); - SK_OUT32(pAC->IoBase, B2_IRQM_MSK, pAC->DynIrqModInfo.MaskIrqModeration); - SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); - if (M_DIMINFO.DisplayStats) { - printk("Enabled interrupt moderation (%i ints/sec)\n", - M_DIMINFO.MaxModIntsPerSec); - } -} +/***************************************************************************** + * + * disableIntMod - disables the interrupt moderation + * + * Description: + * Disabling the interrupt moderation is done by stopping the + * IRQ moderation timer using the B2_IRQM_CTRL register. + * + * Returns: N/A + * + */ +static void disableIntMod( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n")); -/******************************************************************************* -** Function : DisableIntMod() -** Description : Disbles the interrupt moderation independent of what inter- -** rupts are running or not -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : - -** Notes : - -*******************************************************************************/ - -static void -DisableIntMod(SK_AC *pAC) { - - SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP); - if (M_DIMINFO.DisplayStats) { - printk("Disabled interrupt moderation\n"); - } -} + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP); -/******************************************************************************* -** Function : ResizeDimTimerDuration(); -** Description : Checks the current used descriptor ratio and resizes the -** duration timer (longer/smaller) if possible. -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : - -** Notes : There are both maximum and minimum timer duration value. -** This function assumes that interrupt moderation is already -** enabled! -*******************************************************************************/ - -static void -ResizeDimTimerDuration(SK_AC *pAC) { - SK_BOOL IncreaseTimerDuration; - int TotalMaxNbrDescr; - int UsedDescrRatio; - int RatioDiffAbs; - int RatioDiffRel; - int NewMaxModIntsPerSec; - int ModAdjValue; - long ModBase; - - /* - ** Check first if we are allowed to perform any modification - */ - if (IsIntModEnabled(pAC)) { - if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) { - return; - } else { - if (M_DIMINFO.ModJustEnabled) { - M_DIMINFO.ModJustEnabled = SK_FALSE; - return; - } - } - } - - /* - ** If we got until here, we have to evaluate the amount of the - ** descriptor ratio change... - */ - TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC); - UsedDescrRatio = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr; - - if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) { - RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio); - RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio; - M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio; - IncreaseTimerDuration = SK_FALSE; /* in other words: DECREASE */ - } else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) { - RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio); - RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio; - M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio; - IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */ - } else { - RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio); - RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio; - M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio; - IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */ - } - - /* - ** Now we can determine the change in percent - */ - if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) { - ModAdjValue = 1; /* 1% change - maybe some other value in future */ - } else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) { - ModAdjValue = 1; /* 1% change - maybe some other value in future */ - } else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) { - ModAdjValue = 1; /* 1% change - maybe some other value in future */ - } else { - ModAdjValue = 1; /* 1% change - maybe some other value in future */ - } - - if (IncreaseTimerDuration) { - NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec + - (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100; - } else { - NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec - - (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100; - } - - /* - ** Check if we exceed boundaries... - */ - if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) || - (NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) { - if (M_DIMINFO.DisplayStats) { - printk("Cannot change ModTim from %i to %i ints/sec\n", - M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec); - } - return; - } else { - if (M_DIMINFO.DisplayStats) { - printk("Resized ModTim from %i to %i ints/sec\n", - M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec); - } - } - - M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec; - - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { - ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec; - } else { - ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec; - } - - /* - ** We do not need to touch any other registers - */ - SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n")); } /******************************************************************************* -** Function : DisplaySelectedModerationType() -** Description : Displays what type of moderation we have -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : void! -** Notes : - -*******************************************************************************/ - -static void -DisplaySelectedModerationType(SK_AC *pAC) { - - if (pAC->DynIrqModInfo.DisplayStats) { - if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) { - printk("Static int moderation runs with %i INTS/sec\n", - pAC->DynIrqModInfo.MaxModIntsPerSec); - } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) { - if (IsIntModEnabled(pAC)) { - printk("Dynamic int moderation runs with %i INTS/sec\n", - pAC->DynIrqModInfo.MaxModIntsPerSec); - } else { - printk("Dynamic int moderation currently not applied\n"); - } - } else { - printk("No interrupt moderation selected!\n"); - } - } -} - -/******************************************************************************* -** Function : DisplaySelectedModerationMask() -** Description : Displays what interrupts are moderated -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : void! -** Notes : - -*******************************************************************************/ - -static void -DisplaySelectedModerationMask(SK_AC *pAC) { - - if (pAC->DynIrqModInfo.DisplayStats) { - if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) { - switch (pAC->DynIrqModInfo.MaskIrqModeration) { - case IRQ_MASK_TX_ONLY: - printk("Only Tx-interrupts are moderated\n"); - break; - case IRQ_MASK_RX_ONLY: - printk("Only Rx-interrupts are moderated\n"); - break; - case IRQ_MASK_SP_ONLY: - printk("Only special-interrupts are moderated\n"); - break; - case IRQ_MASK_TX_RX: - printk("Tx- and Rx-interrupts are moderated\n"); - break; - case IRQ_MASK_SP_RX: - printk("Special- and Rx-interrupts are moderated\n"); - break; - case IRQ_MASK_SP_TX: - printk("Special- and Tx-interrupts are moderated\n"); - break; - case IRQ_MASK_RX_TX_SP: - printk("All Rx-, Tx and special-interrupts are moderated\n"); - break; - default: - printk("Don't know what is moderated\n"); - break; - } - } else { - printk("No specific interrupts masked for moderation\n"); - } - } -} - -/******************************************************************************* -** Function : DisplayDescrRatio -** Description : Like the name states... -** Programmer : Ralph Roesler -** Last Modified: 23-mar-03 -** Returns : void! -** Notes : - -*******************************************************************************/ - -static void -DisplayDescrRatio(SK_AC *pAC) { - int TotalMaxNbrDescr = 0; - - if (pAC->DynIrqModInfo.DisplayStats) { - TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC); - printk("Ratio descriptors: %i/%i\n", - M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr); - } -} - -/******************************************************************************* -** -** End of file -** -*******************************************************************************/ + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/skethtool.c linux-new/drivers/net/sk98lin/skethtool.c --- linux/drivers/net/sk98lin/skethtool.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-new/drivers/net/sk98lin/skethtool.c 2004-08-26 10:28:00.000000000 +0200 @@ -0,0 +1,1252 @@ +/****************************************************************************** + * + * Name: skethtool.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.3 $ + * Date: $Date: 2004/07/26 15:00:53 $ + * Purpose: All functions regarding ethtool handling + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2004 Marvell. + * + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet + * Server Adapters. + * + * Author: Ralph Roesler (rroesler@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * The technical manual for the adapters is available from SysKonnect's + * web pages: www.syskonnect.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + *****************************************************************************/ + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#include "h/skversion.h" +#include +#include +#include + +/****************************************************************************** + * + * External Functions and Data + * + *****************************************************************************/ + +extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration); +extern void SkDimEnableModerationIfNeeded(SK_AC *pAC); + +/****************************************************************************** + * + * Defines + * + *****************************************************************************/ + +#ifndef ETHT_STATSTRING_LEN +#define ETHT_STATSTRING_LEN 32 +#endif + +#define SK98LIN_STAT(m) sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m) + +#define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ + SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \ + SUPPORTED_TP) + +#define ADV_COPPER_ALL (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ + ADVERTISED_1000baseT_Half| ADVERTISED_1000baseT_Full| \ + ADVERTISED_TP) + +#define SUPP_FIBRE_ALL (SUPPORTED_1000baseT_Full | \ + SUPPORTED_FIBRE | \ + SUPPORTED_Autoneg) + +#define ADV_FIBRE_ALL (ADVERTISED_1000baseT_Full | \ + ADVERTISED_FIBRE | \ + ADVERTISED_Autoneg) + +/****************************************************************************** + * + * Local Function Prototypes + * + *****************************************************************************/ + +#ifdef ETHTOOL_GSET +static void getSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd); +#endif +#ifdef ETHTOOL_SSET +static int setSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd); +#endif +#ifdef ETHTOOL_GPAUSEPARAM +static void getPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause); +#endif +#ifdef ETHTOOL_SPAUSEPARAM +static int setPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause); +#endif +#ifdef ETHTOOL_GDRVINFO +static void getDriverInfo(SK_AC *pAC, int port, struct ethtool_drvinfo *edrvinfo); +#endif +#ifdef ETHTOOL_PHYS_ID +static int startLocateNIC(SK_AC *pAC, int port, struct ethtool_value *blinkSecs); +static void toggleLeds(unsigned long ptr); +#endif +#ifdef ETHTOOL_GCOALESCE +static void getModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc); +#endif +#ifdef ETHTOOL_SCOALESCE +static int setModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc); +#endif +#ifdef ETHTOOL_GWOL +static void getWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol); +#endif +#ifdef ETHTOOL_SWOL +static int setWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol); +#endif + +static int getPortNumber(struct net_device *netdev, struct ifreq *ifr); + +/****************************************************************************** + * + * Local Variables + * + *****************************************************************************/ + +struct sk98lin_stats { + char stat_string[ETHT_STATSTRING_LEN]; + int sizeof_stat; + int stat_offset; +}; + +static struct sk98lin_stats sk98lin_etht_stats_port0[] = { + { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) }, + { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) }, + { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) }, + { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) }, + { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) }, + { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) }, + { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) }, + { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) }, + { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) }, + { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) }, + { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) }, + { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) }, + { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) }, + { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) }, + { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) }, + { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) }, + { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) }, + { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) }, + { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) }, + { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) }, + { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) }, + { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) }, + { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) }, + { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) }, + { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) }, + { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } , + { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) } +}; + +static struct sk98lin_stats sk98lin_etht_stats_port1[] = { + { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) }, + { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) }, + { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) }, + { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) }, + { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) }, + { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) }, + { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) }, + { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) }, + { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) }, + { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) }, + { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) }, + { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) }, + { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) }, + { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) }, + { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) }, + { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) }, + { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) }, + { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) }, + { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) }, + { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) }, + { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) }, + { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) }, + { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) }, + { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) }, + { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) }, + { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } , + { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) } +}; + +#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats) + +static int nbrBlinkQuarterSeconds; +static int currentPortIndex; +static SK_BOOL isLocateNICrunning = SK_FALSE; +static SK_BOOL isDualNetCard = SK_FALSE; +static SK_BOOL doSwitchLEDsOn = SK_FALSE; +static SK_BOOL boardWasDown[2] = { SK_FALSE, SK_FALSE }; +static struct timer_list locateNICtimer; + +/****************************************************************************** + * + * Global Functions + * + *****************************************************************************/ + +/***************************************************************************** + * + * SkEthIoctl - IOCTL entry point for all ethtool queries + * + * Description: + * Any IOCTL request that has to deal with the ethtool command tool is + * dispatched via this function. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +int SkEthIoctl( +struct net_device *netdev, /* the pointer to netdev structure */ +struct ifreq *ifr) /* what interface the request refers to? */ +{ + DEV_NET *pNet = (DEV_NET*) netdev->priv; + SK_AC *pAC = pNet->pAC; + void *pAddr = ifr->ifr_data; + int port = getPortNumber(netdev, ifr); + SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct; + SK_U32 Size = sizeof(SK_PNMI_STRUCT_DATA); + SK_U32 cmd; + struct sk98lin_stats *sk98lin_etht_stats = + (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1; + + if (get_user(cmd, (uint32_t *) pAddr)) { + return -EFAULT; + } + + switch(cmd) { +#ifdef ETHTOOL_GSET + case ETHTOOL_GSET: { + struct ethtool_cmd ecmd = { ETHTOOL_GSET }; + getSettings(pAC, port, &ecmd); + if(copy_to_user(pAddr, &ecmd, sizeof(ecmd))) { + return -EFAULT; + } + return 0; + } + break; +#endif +#ifdef ETHTOOL_SSET + case ETHTOOL_SSET: { + struct ethtool_cmd ecmd; + if(copy_from_user(&ecmd, pAddr, sizeof(ecmd))) { + return -EFAULT; + } + return setSettings(pAC, port, &ecmd); + } + break; +#endif +#ifdef ETHTOOL_GDRVINFO + case ETHTOOL_GDRVINFO: { + struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO }; + getDriverInfo(pAC, port, &drvinfo); + if(copy_to_user(pAddr, &drvinfo, sizeof(drvinfo))) { + return -EFAULT; + } + return 0; + } + break; +#endif +#ifdef ETHTOOL_GSTRINGS + case ETHTOOL_GSTRINGS: { + struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS }; + char *strings = NULL; + int err = 0; + if(copy_from_user(&gstrings, pAddr, sizeof(gstrings))) { + return -EFAULT; + } + switch(gstrings.string_set) { +#ifdef ETHTOOL_GSTATS + case ETH_SS_STATS: { + int i; + gstrings.len = SK98LIN_STATS_LEN; + if ((strings = kmalloc(SK98LIN_STATS_LEN*ETHT_STATSTRING_LEN,GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + for(i=0; i < SK98LIN_STATS_LEN; i++) { + memcpy(&strings[i * ETHT_STATSTRING_LEN], + &(sk98lin_etht_stats[i].stat_string), + ETHT_STATSTRING_LEN); + } + } + break; +#endif + default: + return -EOPNOTSUPP; + } + if(copy_to_user(pAddr, &gstrings, sizeof(gstrings))) { + err = -EFAULT; + } + pAddr += offsetof(struct ethtool_gstrings, data); + if(!err && copy_to_user(pAddr, strings, gstrings.len * ETH_GSTRING_LEN)) { + err = -EFAULT; + } + kfree(strings); + return err; + } +#endif +#ifdef ETHTOOL_GSTATS + case ETHTOOL_GSTATS: { + struct { + struct ethtool_stats eth_stats; + uint64_t data[SK98LIN_STATS_LEN]; + } stats = { {ETHTOOL_GSTATS, SK98LIN_STATS_LEN} }; + int i; + + if (pNet->Up) { + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port); + } + for(i = 0; i < SK98LIN_STATS_LEN; i++) { + if (pNet->Up) { + stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat == + sizeof(uint64_t)) ? + *(uint64_t *)((char *)pAC + + sk98lin_etht_stats[i].stat_offset) : + *(uint32_t *)((char *)pAC + + sk98lin_etht_stats[i].stat_offset); + } else { + stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat == + sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0; + } + } + if(copy_to_user(pAddr, &stats, sizeof(stats))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_PHYS_ID + case ETHTOOL_PHYS_ID: { + struct ethtool_value blinkSecs; + if(copy_from_user(&blinkSecs, pAddr, sizeof(blinkSecs))) { + return -EFAULT; + } + return startLocateNIC(pAC, port, &blinkSecs); + } +#endif +#ifdef ETHTOOL_GPAUSEPARAM + case ETHTOOL_GPAUSEPARAM: { + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM }; + getPauseParams(pAC, port, &epause); + if(copy_to_user(pAddr, &epause, sizeof(epause))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SPAUSEPARAM + case ETHTOOL_SPAUSEPARAM: { + struct ethtool_pauseparam epause; + if(copy_from_user(&epause, pAddr, sizeof(epause))) { + return -EFAULT; + } + return setPauseParams(pAC, port, &epause); + } +#endif +#ifdef ETHTOOL_GSG + case ETHTOOL_GSG: { + struct ethtool_value edata = { ETHTOOL_GSG }; + edata.data = (netdev->features & NETIF_F_SG) != 0; + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SSG + case ETHTOOL_SSG: { + struct ethtool_value edata; + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + if (pAC->ChipsetType) { + /* Don't handle if Genesis chipset */ + if (edata.data) { + netdev->features |= NETIF_F_SG; + } else { + netdev->features &= ~NETIF_F_SG; + } + } + return 0; + } +#endif +#ifdef ETHTOOL_GRXCSUM + case ETHTOOL_GRXCSUM: { + struct ethtool_value edata = { ETHTOOL_GRXCSUM }; + edata.data = pAC->RxPort[port].UseRxCsum; + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SRXCSUM + case ETHTOOL_SRXCSUM: { + struct ethtool_value edata; + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + pAC->RxPort[port].UseRxCsum = edata.data; + return 0; + } +#endif +#ifdef ETHTOOL_GTXCSUM + case ETHTOOL_GTXCSUM: { + struct ethtool_value edata = { ETHTOOL_GTXCSUM }; + edata.data = ((netdev->features & NETIF_F_IP_CSUM) != 0); + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_STXCSUM + case ETHTOOL_STXCSUM: { + struct ethtool_value edata; + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + + if (pAC->ChipsetType) { + /* Don't handle if Genesis chipset */ + if (edata.data) { + netdev->features |= NETIF_F_IP_CSUM; + } else { + netdev->features &= ~NETIF_F_IP_CSUM; + } + } + return 0; + } +#endif +#ifdef ETHTOOL_NWAY_RST + case ETHTOOL_NWAY_RST: { + if(netif_running(netdev)) { + (*netdev->stop)(netdev); + (*netdev->open)(netdev); + } + return 0; + } +#endif +#ifdef NETIF_F_TSO +#ifdef ETHTOOL_GTSO + case ETHTOOL_GTSO: { + struct ethtool_value edata = { ETHTOOL_GTSO }; + edata.data = (netdev->features & NETIF_F_TSO) != 0; + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_STSO + case ETHTOOL_STSO: { + struct ethtool_value edata; + if (CHIP_ID_YUKON_2(pAC)) { + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + if (edata.data) { + netdev->features |= NETIF_F_TSO; + } else { + netdev->features &= ~NETIF_F_TSO; + } + return 0; + } + return -EOPNOTSUPP; + } +#endif +#endif +#ifdef ETHTOOL_GCOALESCE + case ETHTOOL_GCOALESCE: { + struct ethtool_coalesce ecoalesc = { ETHTOOL_GCOALESCE }; + getModerationParams(pAC, port, &ecoalesc); + if(copy_to_user(pAddr, &ecoalesc, sizeof(ecoalesc))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SCOALESCE + case ETHTOOL_SCOALESCE: { + struct ethtool_coalesce ecoalesc; + if(copy_from_user(&ecoalesc, pAddr, sizeof(ecoalesc))) { + return -EFAULT; + } + return setModerationParams(pAC, port, &ecoalesc); + } +#endif +#ifdef ETHTOOL_GWOL + case ETHTOOL_GWOL: { + struct ethtool_wolinfo ewol = { ETHTOOL_GWOL }; + getWOLsettings(pAC, port, &ewol); + if(copy_to_user(pAddr, &ewol, sizeof(ewol))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SWOL + case ETHTOOL_SWOL: { + struct ethtool_wolinfo ewol; + if(copy_from_user(&ewol, pAddr, sizeof(ewol))) { + return -EFAULT; + } + return setWOLsettings(pAC, port, &ewol); + } +#endif + default: + return -EOPNOTSUPP; + } +} /* SkEthIoctl() */ + +/****************************************************************************** + * + * Local Functions + * + *****************************************************************************/ + +#ifdef ETHTOOL_GSET +/***************************************************************************** + * + * getSettings - retrieves the current settings of the selected adapter + * + * Description: + * The current configuration of the selected adapter is returned. + * This configuration involves a)speed, b)duplex and c)autoneg plus + * a number of other variables. + * + * Returns: N/A + * + */ +static void getSettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_cmd *ecmd) /* mandatory command structure for results */ +{ + SK_GEPORT *pPort = &pAC->GIni.GP[port]; + + static int DuplexAutoNegConfMap[9][3]= { + { -1 , -1 , -1 }, + { 0 , -1 , -1 }, + { SK_LMODE_HALF , DUPLEX_HALF, AUTONEG_DISABLE }, + { SK_LMODE_FULL , DUPLEX_FULL, AUTONEG_DISABLE }, + { SK_LMODE_AUTOHALF , DUPLEX_HALF, AUTONEG_ENABLE }, + { SK_LMODE_AUTOFULL , DUPLEX_FULL, AUTONEG_ENABLE }, + { SK_LMODE_AUTOBOTH , DUPLEX_FULL, AUTONEG_ENABLE }, + { SK_LMODE_AUTOSENSE , -1 , -1 }, + { SK_LMODE_INDETERMINATED, -1 , -1 } + }; + + static int SpeedConfMap[6][2] = { + { 0 , -1 }, + { SK_LSPEED_AUTO , SPEED_1000 }, + { SK_LSPEED_10MBPS , SPEED_10 }, + { SK_LSPEED_100MBPS , SPEED_100 }, + { SK_LSPEED_1000MBPS , SPEED_1000 }, + { SK_LSPEED_INDETERMINATED, 0 } + }; + + ecmd->phy_address = port; + ecmd->speed = SpeedConfMap[pPort->PLinkSpeedUsed][1]; + ecmd->duplex = DuplexAutoNegConfMap[pPort->PLinkModeStatus][1]; + ecmd->autoneg = DuplexAutoNegConfMap[pPort->PLinkModeStatus][2]; + ecmd->transceiver = XCVR_INTERNAL; + + if (pAC->GIni.GICopperType) { + ecmd->port = PORT_TP; + ecmd->supported = (SUPP_COPPER_ALL|SUPPORTED_Autoneg); + ecmd->advertising = (ADV_COPPER_ALL); + if (ecmd->autoneg == AUTONEG_ENABLE) { + ecmd->advertising |= ADVERTISED_Autoneg; + } + } else { + ecmd->port = PORT_FIBRE; + ecmd->supported = (SUPP_FIBRE_ALL); + ecmd->advertising = (ADV_FIBRE_ALL); + } +} +#endif + +#ifdef ETHTOOL_SSET +/***************************************************************************** + * + * setSettings - configures the settings of a selected adapter + * + * Description: + * Possible settings that may be altered are a)speed, b)duplex or + * c)autonegotiation. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setSettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_cmd *ecmd) /* command structure containing settings */ +{ + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv; + SK_U32 Instance; + char Buf[4]; + unsigned int Len = 1; + int Ret; + + if (port == 0) { + Instance = (pAC->RlmtNets == 2) ? 1 : 2; + } else { + Instance = (pAC->RlmtNets == 2) ? 2 : 3; + } + + if (ecmd->autoneg == AUTONEG_DISABLE) { + if (ecmd->duplex == DUPLEX_FULL) { + *Buf = (char) SK_LMODE_FULL; + } else { + *Buf = (char) SK_LMODE_HALF; + } + } else { + if (ecmd->duplex == DUPLEX_FULL) { + *Buf = (char) SK_LMODE_AUTOFULL; + } else { + *Buf = (char) SK_LMODE_AUTOHALF; + } + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + return -EINVAL; + } + + if (ecmd->speed == SPEED_1000) { + *Buf = (char) SK_LSPEED_1000MBPS; + } else if (ecmd->speed == SPEED_100) { + *Buf = (char) SK_LSPEED_100MBPS; + } else { + *Buf = (char) SK_LSPEED_10MBPS; + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + return -EINVAL; + } + return 0; +} +#endif + +#ifdef ETHTOOL_GPAUSEPARAM +/***************************************************************************** + * + * getPauseParams - retrieves the pause parameters + * + * Description: + * All current pause parameters of a selected adapter are placed + * in the passed ethtool_pauseparam structure and are returned. + * + * Returns: N/A + * + */ +static void getPauseParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_pauseparam *epause) /* pause parameter struct for result */ +{ + SK_GEPORT *pPort = &pAC->GIni.GP[port]; + SK_BOOL isAutoNegEnabled = SK_TRUE; + + if (pPort->PLinkModeConf == SK_LMODE_HALF || + pPort->PLinkModeConf == SK_LMODE_FULL) { + isAutoNegEnabled = SK_FALSE; + } + + epause->autoneg = isAutoNegEnabled; + epause->rx_pause = 0; + epause->tx_pause = 0; + + if (isAutoNegEnabled) { + if (pPort->PFlowCtrlMode & SK_FLOW_MODE_LOC_SEND) { + epause->tx_pause = 1; + } + if ((pPort->PFlowCtrlMode & SK_FLOW_MODE_SYMMETRIC) || + (pPort->PFlowCtrlMode & SK_FLOW_MODE_SYM_OR_REM)) { + epause->tx_pause = 1; + epause->rx_pause = 1; + } + } +} +#endif + +#ifdef ETHTOOL_SPAUSEPARAM +/***************************************************************************** + * + * setPauseParams - configures the pause parameters of an adapter + * + * Description: + * This function sets the Rx or Tx pause parameters + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setPauseParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_pauseparam *epause) /* pause parameter struct with params */ +{ + SK_GEPORT *pPort = &pAC->GIni.GP[port]; + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv; + int PrevSpeedVal = pPort->PLinkSpeedUsed; + + SK_U32 Instance; + char Buf[4]; + unsigned int Len = 1; + int Ret; + + if (port == 0) { + Instance = (pAC->RlmtNets == 2) ? 1 : 2; + } else { + Instance = (pAC->RlmtNets == 2) ? 2 : 3; + } + + if (epause->autoneg == AUTONEG_DISABLE) { + if (pPort->PLinkModeConf == SK_LMODE_AUTOHALF) { + *Buf = (char) SK_LMODE_HALF; + } + if ((pPort->PLinkModeConf == SK_LMODE_AUTOFULL) || + (pPort->PLinkModeConf == SK_LMODE_AUTOBOTH)) { + *Buf = (char) SK_LMODE_FULL; + } + } + + if (epause->autoneg == AUTONEG_ENABLE) { + if (pPort->PLinkModeConf == SK_LMODE_HALF) { + // pPort->PLinkModeConf = SK_LMODE_AUTOHALF; + *Buf = (char) SK_LMODE_AUTOHALF; + } + if (pPort->PLinkModeConf == SK_LMODE_FULL) { + // pPort->PLinkModeConf = SK_LMODE_AUTOBOTH; + *Buf = (char) SK_LMODE_AUTOBOTH; + } + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + printk("ethtool: error changing autoneg parameter\n"); + } + + if(epause->rx_pause && epause->tx_pause) { + // pPort->PFlowCtrlMode = SK_FLOW_MODE_SYMMETRIC; + *Buf = (char) SK_FLOW_MODE_SYMMETRIC; + } else if (epause->rx_pause && !epause->tx_pause) { + // pPort->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + *Buf = (char) SK_FLOW_MODE_SYM_OR_REM; + } else if(!epause->rx_pause && epause->tx_pause) { + // pPort->PFlowCtrlMode = SK_FLOW_MODE_LOC_SEND; + *Buf = (char) SK_FLOW_MODE_LOC_SEND; + } else { + // pPort->PFlowCtrlMode = SK_FLOW_MODE_NONE; + *Buf = (char) SK_FLOW_MODE_NONE; + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + printk("ethtool: error changing rx/tx pause parameters\n"); + } + + /* + ** It may be that autoneg has been disabled! Therefore set + ** the speed to the previously used value... + */ + if (epause->autoneg == AUTONEG_DISABLE) { + if ((PrevSpeedVal == SK_LSPEED_AUTO) || + (PrevSpeedVal == SK_LSPEED_INDETERMINATED)) { + PrevSpeedVal = SK_LSPEED_100MBPS; + } + *Buf = (char) PrevSpeedVal; + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + printk("ethtool: setting the speed parameter\n"); + } + } + return 0; +} +#endif + +#ifdef ETHTOOL_GCOALESCE +/***************************************************************************** + * + * getModerationParams - retrieves the IRQ moderation settings + * + * Description: + * All current IRQ moderation settings of a selected adapter are placed + * in the passed ethtool_coalesce structure and are returned. + * + * Returns: N/A + * + */ +static void getModerationParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct for results */ +{ + DIM_INFO *Info = &pAC->DynIrqModInfo; + SK_BOOL UseTxIrqModeration = SK_FALSE; + SK_BOOL UseRxIrqModeration = SK_FALSE; + + if (Info->IntModTypeSelect != C_INT_MOD_NONE) { + if (CHIP_ID_YUKON_2(pAC)) { + UseRxIrqModeration = SK_TRUE; + UseTxIrqModeration = SK_TRUE; + } else { + if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) || + (Info->MaskIrqModeration == IRQ_MASK_SP_RX) || + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) { + UseRxIrqModeration = SK_TRUE; + } + if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) || + (Info->MaskIrqModeration == IRQ_MASK_SP_TX) || + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) { + UseTxIrqModeration = SK_TRUE; + } + } + + if (UseRxIrqModeration) { + ecoalesc->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec; + } + if (UseTxIrqModeration) { + ecoalesc->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec; + } + if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) { + ecoalesc->rate_sample_interval = Info->DynIrqModSampleInterval; + if (UseRxIrqModeration) { + ecoalesc->use_adaptive_rx_coalesce = 1; + ecoalesc->rx_coalesce_usecs_low = + 1000000 / Info->MaxModIntsPerSecLowerLimit; + ecoalesc->rx_coalesce_usecs_high = + 1000000 / Info->MaxModIntsPerSecUpperLimit; + } + if (UseTxIrqModeration) { + ecoalesc->use_adaptive_tx_coalesce = 1; + ecoalesc->tx_coalesce_usecs_low = + 1000000 / Info->MaxModIntsPerSecLowerLimit; + ecoalesc->tx_coalesce_usecs_high = + 1000000 / Info->MaxModIntsPerSecUpperLimit; + } + } + } +} +#endif + +#ifdef ETHTOOL_SCOALESCE +/***************************************************************************** + * + * setModerationParams - configures the IRQ moderation of an adapter + * + * Description: + * Depending on the desired IRQ moderation parameters, either a) static, + * b) dynamic or c) no moderation is configured. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setModerationParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct with params */ +{ + DIM_INFO *Info = &pAC->DynIrqModInfo; + int PrevModeration = Info->IntModTypeSelect; + + if ((ecoalesc->rx_coalesce_usecs) || (ecoalesc->tx_coalesce_usecs)) { + if (!CHIP_ID_YUKON_2(pAC)) { + if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) || + (Info->MaskIrqModeration == IRQ_MASK_SP_TX) || + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) { + Info->MaskIrqModeration = IRQ_MASK_SP_ONLY; + } + } + Info->IntModTypeSelect = C_INT_MOD_STATIC; + if (ecoalesc->rx_coalesce_usecs) { + Info->MaxModIntsPerSec = + 1000000 / ecoalesc->rx_coalesce_usecs; + if (!CHIP_ID_YUKON_2(pAC)) { + if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_TX_RX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_SP_RX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) { + Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP; + } + } else { + Info->MaskIrqModeration = Y2_IRQ_MASK; + } + } + if (ecoalesc->tx_coalesce_usecs) { + Info->MaxModIntsPerSec = + 1000000 / ecoalesc->tx_coalesce_usecs; + if (!CHIP_ID_YUKON_2(pAC)) { + if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_TX_RX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_SP_TX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) { + Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP; + } + } else { + Info->MaskIrqModeration = Y2_IRQ_MASK; + } + } + if ((ecoalesc->rate_sample_interval) || + (ecoalesc->rx_coalesce_usecs_low) || + (ecoalesc->tx_coalesce_usecs_low) || + (ecoalesc->rx_coalesce_usecs_high)|| + (ecoalesc->tx_coalesce_usecs_high)) { + Info->IntModTypeSelect = C_INT_MOD_DYNAMIC; + if (ecoalesc->rate_sample_interval) { + Info->DynIrqModSampleInterval = + ecoalesc->rate_sample_interval; + } + if (ecoalesc->rx_coalesce_usecs_low) { + Info->MaxModIntsPerSecLowerLimit = + 1000000 / ecoalesc->rx_coalesce_usecs_low; + } + if (ecoalesc->tx_coalesce_usecs_low) { + Info->MaxModIntsPerSecLowerLimit = + 1000000 / ecoalesc->tx_coalesce_usecs_low; + } + if (ecoalesc->rx_coalesce_usecs_high) { + Info->MaxModIntsPerSecUpperLimit = + 1000000 / ecoalesc->rx_coalesce_usecs_high; + } + if (ecoalesc->tx_coalesce_usecs_high) { + Info->MaxModIntsPerSecUpperLimit = + 1000000 / ecoalesc->tx_coalesce_usecs_high; + } + } + } else { + Info->IntModTypeSelect = C_INT_MOD_NONE; + } + + if ((PrevModeration == C_INT_MOD_NONE) && + (Info->IntModTypeSelect != C_INT_MOD_NONE)) { + SkDimEnableModerationIfNeeded(pAC); + } + if ((PrevModeration != C_INT_MOD_NONE) && + (Info->IntModTypeSelect == C_INT_MOD_NONE)) { + SkDimDisableModeration(pAC, PrevModeration); + } + + return 0; +} +#endif + +#ifdef ETHTOOL_GWOL +/***************************************************************************** + * + * getWOLsettings - retrieves the WOL settings of the selected adapter + * + * Description: + * All current WOL settings of a selected adapter are placed in the + * passed ethtool_wolinfo structure and are returned to the caller. + * + * Returns: N/A + * + */ +static void getWOLsettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_wolinfo *ewol) /* mandatory WOL structure for results */ +{ + ewol->supported = + WAKE_PHY|WAKE_MAGIC|WAKE_UCAST|WAKE_MCAST|WAKE_BCAST; + + ewol->wolopts = + WAKE_PHY|WAKE_MAGIC|WAKE_UCAST|WAKE_MCAST|WAKE_BCAST; + + return; +} +#endif + +#ifdef ETHTOOL_SWOL +/***************************************************************************** + * + * setWOLsettings - configures the WOL settings of a selected adapter + * + * Description: + * The WOL settings of a selected adapter are configured regarding + * the parameters in the passed ethtool_wolinfo structure. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setWOLsettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_wolinfo *ewol) /* WOL structure containing settings */ +{ + return 0; +} +#endif + +#ifdef ETHTOOL_GDRVINFO +/***************************************************************************** + * + * getDriverInfo - returns generic driver and adapter information + * + * Description: + * Generic driver information is returned via this function, such as + * the name of the driver, its version and and firmware version. + * In addition to this, the location of the selected adapter is + * returned as a bus info string (e.g. '01:05.0'). + * + * Returns: N/A + * + */ +static void getDriverInfo( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_drvinfo *edrvinfo) /* mandatory info structure for results */ +{ + char versionString[32]; + + snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL); + strncpy(edrvinfo->driver, DRIVER_FILE_NAME , 32); + strncpy(edrvinfo->version, versionString , 32); + strncpy(edrvinfo->fw_version, "N/A", 32); + strncpy(edrvinfo->bus_info, pAC->PciDev->slot_name, 32); +#ifdef ETHTOOL_GSTATS + edrvinfo->n_stats = SK98LIN_STATS_LEN; +#endif +} +#endif + +#ifdef ETHTOOL_PHYS_ID +/***************************************************************************** + * + * startLocateNIC - start the locate NIC feature of the elected adapter + * + * Description: + * This function is used if the user want to locate a particular NIC. + * All LEDs are regularly switched on and off, so the NIC can easily + * be identified. + * + * Returns: + * ==0: everything fine, no error, locateNIC test was started + * !=0: one locateNIC test runs already + * + */ +static int startLocateNIC( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_value *blinkSecs) /* how long the LEDs should blink in seconds */ +{ + struct SK_NET_DEVICE *pDev = pAC->dev[port]; + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv; + int OtherPort = (port) ? 0 : 1; + struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort]; + DEV_NET *pOtherNet = (DEV_NET *) pAC->dev[OtherPort]->priv; + + if (isLocateNICrunning) { + return -EFAULT; + } + isLocateNICrunning = SK_TRUE; + currentPortIndex = port; + isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE; + + if (!pNet->Up) { + (*pDev->open)(pDev); + boardWasDown[0] = SK_TRUE; + } else { + boardWasDown[0] = SK_FALSE; + } + + if (isDualNetCard) { + if (!pOtherNet->Up) { + (*pOtherDev->open)(pOtherDev); + boardWasDown[1] = SK_TRUE; + } else { + boardWasDown[1] = SK_FALSE; + } + } + + if ((blinkSecs->data < 1) || (blinkSecs->data > 30)) { + blinkSecs->data = 3; /* three seconds default */ + } + nbrBlinkQuarterSeconds = 4*blinkSecs->data; + + init_timer(&locateNICtimer); + locateNICtimer.function = toggleLeds; + locateNICtimer.data = (unsigned long) pAC; + locateNICtimer.expires = jiffies + 1*HZ; /* initially 1sec */ + add_timer(&locateNICtimer); + + return 0; +} + +/***************************************************************************** + * + * toggleLeds - Changes the LED state of an adapter + * + * Description: + * This function changes the current state of all LEDs of an adapter so + * that it can be located by a user. If the requested time interval for + * this test has elapsed, this function cleans up everything that was + * temporarily setup during the locate NIC test. This involves of course + * also closing or opening any adapter so that the initial board state + * is recovered. + * + * Returns: N/A + * + */ +static void toggleLeds( +unsigned long ptr) /* holds the pointer to adapter control context */ +{ + SK_AC *pAC = (SK_AC *) ptr; + int port = currentPortIndex; + SK_IOC IoC = pAC->IoBase; + struct SK_NET_DEVICE *pDev = pAC->dev[port]; + int OtherPort = (port) ? 0 : 1; + struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort]; + + SK_U16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) | + PHY_M_LED_MO_10(MO_LED_ON) | + PHY_M_LED_MO_100(MO_LED_ON) | + PHY_M_LED_MO_1000(MO_LED_ON) | + PHY_M_LED_MO_RX(MO_LED_ON)); + SK_U16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) | + PHY_M_LED_MO_10(MO_LED_OFF) | + PHY_M_LED_MO_100(MO_LED_OFF) | + PHY_M_LED_MO_1000(MO_LED_OFF) | + PHY_M_LED_MO_RX(MO_LED_OFF)); + + nbrBlinkQuarterSeconds--; + if (nbrBlinkQuarterSeconds <= 0) { + (*pDev->stop)(pDev); + if (isDualNetCard) { + (*pOtherDev->stop)(pOtherDev); + } + + if (!boardWasDown[0]) { + (*pDev->open)(pDev); + } + if (isDualNetCard) { + (*pOtherDev->open)(pOtherDev); + } + isDualNetCard = SK_FALSE; + isLocateNICrunning = SK_FALSE; + return; + } + + doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE; + if (doSwitchLEDsOn) { + if (pAC->GIni.GIGenesis) { + SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON); + SkGeYellowLED(pAC,IoC,LED_ON >> 1); + SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST); + if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) { + SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON); + } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) { + SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800); + } else { + SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST); + } + } else { + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0); + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn); + } + } else { + if (pAC->GIni.GIGenesis) { + SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF); + SkGeYellowLED(pAC,IoC,LED_OFF >> 1); + SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS); + if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) { + SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF); + } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) { + SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT); + } else { + SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS); + } + } else { + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0); + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff); + } + } + + locateNICtimer.function = toggleLeds; + locateNICtimer.data = (unsigned long) pAC; + locateNICtimer.expires = jiffies + (1*HZ)/4; /* 250ms */ + add_timer(&locateNICtimer); +} +#endif + +/***************************************************************************** + * + * getPortNumber - evaluates the port number of an interface + * + * Description: + * It may be that the current interface refers to one which is located + * on a dual net adapter. Hence, this function will return the correct + * port for further use. + * + * Returns: + * the port number that corresponds to the selected adapter + * + */ +static int getPortNumber( +struct net_device *netdev, /* the pointer to netdev structure */ +struct ifreq *ifr) /* what interface the request refers to? */ +{ + DEV_NET *pNet = (DEV_NET*) netdev->priv; + SK_AC *pAC = pNet->pAC; + + if (pAC->dev[1] != pAC->dev[0]) { + if (!strcmp(pAC->dev[1]->name, ifr->ifr_name)) { + return 1; /* port index 1 */ + } + } + return 0; +} + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/skge.c linux-new/drivers/net/sk98lin/skge.c --- linux/drivers/net/sk98lin/skge.c 2004-09-07 13:32:43.545367750 +0200 +++ linux-new/drivers/net/sk98lin/skge.c 2004-08-26 10:28:00.000000000 +0200 @@ -1,25 +1,23 @@ /****************************************************************************** * - * Name: skge.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.45 $ - * Date: $Date: 2004/02/12 14:41:02 $ - * Purpose: The main driver source module + * Name: skge.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.60 $ + * Date: $Date: 2004/08/25 13:24:55 $ + * Purpose: The main driver source module * ******************************************************************************/ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect GmbH. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet * Server Adapters. * - * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and - * SysKonnects GEnesis Solaris driver - * Author: Christoph Goos (cgoos@syskonnect.de) - * Mirko Lindner (mlindner@syskonnect.de) + * Author: Mirko Lindner (mlindner@syskonnect.de) + * Ralph Roesler (rroesler@syskonnect.de) * * Address all question to: linux@syskonnect.de * @@ -38,71 +36,33 @@ /****************************************************************************** * - * Possible compiler options (#define xxx / -Dxxx): - * - * debugging can be enable by changing SK_DEBUG_CHKMOD and - * SK_DEBUG_CHKCAT in makefile (described there). - * - ******************************************************************************/ - -/****************************************************************************** - * * Description: * - * This is the main module of the Linux GE driver. - * - * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h - * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters. - * Those are used for drivers on multiple OS', so some thing may seem - * unnecessary complicated on Linux. Please do not try to 'clean up' - * them without VERY good reasons, because this will make it more - * difficult to keep the Linux driver in synchronisation with the - * other versions. - * - * Include file hierarchy: - * - * - * - * "h/skdrv1st.h" - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * those three depending on kernel version used: - * - * - * - * - * - * "h/skerror.h" - * "h/skdebug.h" - * "h/sktypes.h" - * "h/lm80.h" - * "h/xmac_ii.h" - * - * "h/skdrv2nd.h" - * "h/skqueue.h" - * "h/skgehwt.h" - * "h/sktimer.h" - * "h/ski2c.h" - * "h/skgepnmi.h" - * "h/skvpd.h" - * "h/skgehw.h" - * "h/skgeinit.h" - * "h/skaddr.h" - * "h/skgesirq.h" - * "h/skcsum.h" - * "h/skrlmt.h" + * All source files in this sk98lin directory except of the sk98lin + * Linux specific files + * + * - skdim.c + * - skethtool.c + * - skge.c + * - skproc.c + * - sky2.c + * - Makefile + * - h/skdrv1st.h + * - h/skdrv2nd.h + * - h/sktypes.h + * - h/skversion.h + * + * are part of SysKonnect's common modules for the SK-9xxx adapters. + * + * Those common module files which are not Linux specific are used to + * build drivers on different OS' (e.g. Windows, MAC OS) so that those + * drivers are based on the same set of files + * + * At a first glance, this seems to complicate things unnescessarily on + * Linux, but please do not try to 'clean up' them without VERY good + * reasons, because this will make it more difficult to keep the sk98lin + * driver for Linux in synchronisation with the other drivers running on + * other operating systems. * ******************************************************************************/ @@ -110,7 +70,11 @@ #include #include +#include + +#ifdef CONFIG_PROC_FS #include +#endif #include "h/skdrv1st.h" #include "h/skdrv2nd.h" @@ -130,22 +94,17 @@ /* use the receive hw checksum driver functionality */ #define USE_SK_RX_CHECKSUM -/* use the scatter-gather functionality with sendfile() */ -#define SK_ZEROCOPY - -/* use of a transmit complete interrupt */ -#define USE_TX_COMPLETE +/* use TCP segmentation offload if possible */ +#define USE_SK_TSO_FEATURE -/* - * threshold for copying small receive frames - * set to 0 to avoid copying, set to 9001 to copy all frames - */ -#define SK_COPY_THRESHOLD 50 +/* threshold for copying small RX frames; 0 avoids copying, 9001 copies all */ +#define SK_COPY_THRESHOLD 50 /* number of adapters that can be configured via command line params */ -#define SK_MAX_CARD_PARAM 16 - +#define SK_MAX_CARD_PARAM 16 +/* use of a transmit complete interrupt */ +/* #define USE_TX_COMPLETE */ /* * use those defines for a compile-in version of the driver instead @@ -165,21 +124,13 @@ // #define CON_TYPE {"Auto", } // #define RLMT_MODE {"CheckLinkState", } -#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb) -#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb) -#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb) - - /* Set blink mode*/ #define OEM_CONFIG_VALUE ( SK_ACT_LED_BLINK | \ SK_DUP_LED_NORMAL | \ SK_LED_LINK100_ON) - -/* Isr return value */ -#define SkIsrRetVar irqreturn_t -#define SkIsrRetNone IRQ_NONE -#define SkIsrRetHandled IRQ_HANDLED +#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F) +#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F) /******************************************************************************* @@ -188,12 +139,22 @@ * ******************************************************************************/ +static int __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent); +static void sk98lin_remove_device(struct pci_dev *pdev); +#ifdef SK_CONFIG_PM +static int sk98lin_suspend(struct pci_dev *pdev, uint32_t state); +static int sk98lin_resume(struct pci_dev *pdev); +static void SkHWSetDState(SK_AC *pAC, SK_IOC IoC, SK_DEVICE_POWER_STATE State); +static void SkHWSwitchPower(SK_AC *pAC, SK_IOC IoC, SK_DEVICE_POWER_STATE State); +static int SkSetPortSpeed(SK_AC *pAC, SK_IOC IoC, SK_U8 Speed); +static void SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr); +#endif static void FreeResources(struct SK_NET_DEVICE *dev); static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC); static SK_BOOL BoardAllocMem(SK_AC *pAC); static void BoardFreeMem(SK_AC *pAC); static void BoardInitMem(SK_AC *pAC); -static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, SK_BOOL); +static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL); static SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); static int SkGeOpen(struct SK_NET_DEVICE *dev); @@ -209,24 +170,22 @@ static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*); static void FillRxRing(SK_AC*, RX_PORT*); static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*); +#ifdef CONFIG_SK98LIN_NAPI +static int SkGePoll(struct net_device *dev, int *budget); +static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int); +#else static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); -static void ClearAndStartRx(SK_AC*, int); -static void ClearTxIrq(SK_AC*, int, int); +#endif static void ClearRxRing(SK_AC*, RX_PORT*); static void ClearTxRing(SK_AC*, TX_PORT*); static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu); static void PortReInitBmu(SK_AC*, int); static int SkGeIocMib(DEV_NET*, unsigned int, int); static int SkGeInitPCI(SK_AC *pAC); -static void StartDrvCleanupTimer(SK_AC *pAC); -static void StopDrvCleanupTimer(SK_AC *pAC); -static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*); - -#ifdef SK_DIAG_SUPPORT static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName); static int SkDrvInitAdapter(SK_AC *pAC, int devNbr); static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr); -#endif +static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*); /******************************************************************************* * @@ -234,17 +193,33 @@ * ******************************************************************************/ -#ifdef CONFIG_PROC_FS -static const char SK_Root_Dir_entry[] = "sk98lin"; -static struct proc_dir_entry *pSkRootDir; -extern struct file_operations sk_proc_fops; +extern SK_BOOL SkY2AllocateResources(SK_AC *pAC); +extern void SkY2FreeResources(SK_AC *pAC); +extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port); +extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port); +extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port); +extern SkIsrRetVar SkY2Isr(int irq,void *dev_id,struct pt_regs *ptregs); +extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev); +extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode); +extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port); +extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage); +extern void SkY2RestartStatusUnit(SK_AC *pAC); +#ifdef CONFIG_SK98LIN_NAPI +extern int SkY2Poll(struct net_device *dev, int *budget); #endif extern void SkDimEnableModerationIfNeeded(SK_AC *pAC); -extern void SkDimDisplayModerationSettings(SK_AC *pAC); extern void SkDimStartModerationTimer(SK_AC *pAC); extern void SkDimModerate(SK_AC *pAC); +extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr); + +#ifdef CONFIG_PROC_FS +static const char SK_Root_Dir_entry[] = "sk98lin"; +static struct proc_dir_entry *pSkRootDir; +extern struct file_operations sk_proc_fops; +#endif + #ifdef DEBUG static void DumpMsg(struct sk_buff*, char*); static void DumpData(char*, int); @@ -252,12 +227,375 @@ #endif /* global variables *********************************************************/ +static const char *BootString = BOOT_STRING; struct SK_NET_DEVICE *SkGeRootDev = NULL; static SK_BOOL DoPrintInterfaceChange = SK_TRUE; /* local variables **********************************************************/ static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}}; static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480}; +static int sk98lin_max_boards_found = 0; + +#ifdef CONFIG_PROC_FS +static struct proc_dir_entry *pSkRootDir; +#endif + + + +static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = { +/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! * + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */ + { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl); + +static struct pci_driver sk98lin_driver = { + .name = DRIVER_FILE_NAME, + .id_table = sk98lin_pci_tbl, + .probe = sk98lin_init_device, + .remove = __devexit_p(sk98lin_remove_device), +#ifdef SK_CONFIG_PM + .suspend = sk98lin_suspend, + .resume = sk98lin_resume +#endif +}; + + +/***************************************************************************** + * + * sk98lin_init_device - initialize the adapter + * + * Description: + * This function initializes the adapter. Resources for + * the adapter are allocated and the adapter is brought into Init 1 + * state. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int __devinit sk98lin_init_device(struct pci_dev *pdev, + const struct pci_device_id *ent) + +{ + static SK_BOOL sk98lin_boot_string = SK_FALSE; + static SK_BOOL sk98lin_proc_entry = SK_FALSE; + static int sk98lin_boards_found = 0; + SK_AC *pAC; + DEV_NET *pNet = NULL; + struct SK_NET_DEVICE *dev = NULL; + int retval; +#ifdef CONFIG_PROC_FS + struct proc_dir_entry *pProcFile; +#endif + + retval = pci_enable_device(pdev); + if (retval) { + printk(KERN_ERR "Cannot enable PCI device, " + "aborting.\n"); + return retval; + } + + dev = NULL; + pNet = NULL; + + + /* INSERT * We have to find the power-management capabilities */ + /* Find power-management capability. */ + + + + /* Configure DMA attributes. */ + retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL); + if (!retval) { + retval = pci_set_dma_mask(pdev, (u64) 0xffffffff); + if (retval) + return retval; + } else { + return retval; + } + + + if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + return -ENODEV; + } + + pNet = dev->priv; + pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); + if (pNet->pAC == NULL){ + free_netdev(dev); + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + return -ENODEV; + } + + + /* Print message */ + if (!sk98lin_boot_string) { + /* set display flag to TRUE so that */ + /* we only display this string ONCE */ + sk98lin_boot_string = SK_TRUE; + printk("%s\n", BootString); + } + + memset(pNet->pAC, 0, sizeof(SK_AC)); + pAC = pNet->pAC; + pAC->PciDev = pdev; + pAC->PciDevId = pdev->device; + pAC->dev[0] = dev; + pAC->dev[1] = dev; + sprintf(pAC->Name, "SysKonnect SK-98xx"); + pAC->CheckQueue = SK_FALSE; + + pNet->Mtu = 1500; + pNet->Up = 0; + dev->irq = pdev->irq; + retval = SkGeInitPCI(pAC); + if (retval) { + printk("SKGE: PCI setup failed: %i\n", retval); + free_netdev(dev); + return -ENODEV; + } + + SET_MODULE_OWNER(dev); + + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->get_stats = &SkGeStats; + dev->last_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; + SET_NETDEV_DEV(dev, &pdev->dev); + + pAC->Index = sk98lin_boards_found; + + if (SkGeBoardInit(dev, pAC)) { + free_netdev(dev); + return -ENODEV; + } else { + ProductStr(pAC); + } + + /* shifter to later moment in time... */ + if (CHIP_ID_YUKON_2(pAC)) { + dev->hard_start_xmit = &SkY2Xmit; + } else { + dev->hard_start_xmit = &SkGeXmit; + } + +#ifdef NETIF_F_TSO +#ifdef USE_SK_TSO_FEATURE + if (CHIP_ID_YUKON_2(pAC)) { + dev->features |= NETIF_F_TSO; + } +#endif +#endif +#ifdef CONFIG_SK98LIN_ZEROCOPY + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_SG; +#endif +#ifdef USE_SK_TX_CHECKSUM + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_IP_CSUM; +#endif +#ifdef USE_SK_RX_CHECKSUM + pAC->RxPort[0].UseRxCsum = SK_TRUE; +#endif + + /* Save the hardware revision */ + pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + + (pAC->GIni.GIPciHwRev & 0x0F); + + /* Set driver globals */ + pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME; + pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE; + + SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA)); + SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct), + sizeof(SK_PNMI_STRUCT_DATA)); + + /* Register net device */ + retval = register_netdev(dev); + if (retval) { + printk(KERN_ERR "SKGE: Could not register device.\n"); + FreeResources(dev); + free_netdev(dev); + return retval; + } + + /* Save initial device name */ + strcpy(pNet->InitialDevName, dev->name); + + /* Print adapter specific string from vpd and config settings */ + printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr); + printk(" PrefPort:%c RlmtMode:%s\n", + 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, + (pAC->RlmtMode==0) ? "Check Link State" : + ((pAC->RlmtMode==1) ? "Check Link State" : + ((pAC->RlmtMode==3) ? "Check Local Port" : + ((pAC->RlmtMode==7) ? "Check Segmentation" : + ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); + + SkGeYellowLED(pAC, pAC->IoBase, 1); + + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); + + /* First adapter... Create proc and print message */ +#ifdef CONFIG_PROC_FS + if (!sk98lin_proc_entry) { + sk98lin_proc_entry = SK_TRUE; + SK_MEMCPY(&SK_Root_Dir_entry, BootString, + sizeof(SK_Root_Dir_entry) - 1); + + /*Create proc (directory)*/ + if(!pSkRootDir) { + pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net); + if (!pSkRootDir) { + printk(KERN_WARNING "%s: Unable to create /proc/net/%s", + dev->name, SK_Root_Dir_entry); + } else { + pSkRootDir->owner = THIS_MODULE; + } + } + } + + /* Create proc file */ + if (pSkRootDir && + (pProcFile = create_proc_entry(pNet->InitialDevName, S_IRUGO, + pSkRootDir))) { + pProcFile->proc_fops = &sk_proc_fops; + pProcFile->data = dev; + } + +#endif + + pNet->PortNr = 0; + pNet->NetNr = 0; + + sk98lin_boards_found++; + pci_set_drvdata(pdev, dev); + + /* More then one port found */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { + if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + return -ENODEV; + } + + pAC->dev[1] = dev; + pNet = dev->priv; + pNet->PortNr = 1; + pNet->NetNr = 1; + pNet->pAC = pAC; + pNet->Mtu = 1500; + pNet->Up = 0; + + if (CHIP_ID_YUKON_2(pAC)) { + dev->hard_start_xmit = &SkY2Xmit; + } else { + dev->hard_start_xmit = &SkGeXmit; + } + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->get_stats = &SkGeStats; + dev->last_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; + +#ifdef NETIF_F_TSO +#ifdef USE_SK_TSO_FEATURE + if (CHIP_ID_YUKON_2(pAC)) { + dev->features |= NETIF_F_TSO; + } +#endif +#endif +#ifdef CONFIG_SK98LIN_ZEROCOPY + /* Don't handle if Genesis chipset */ + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_SG; +#endif +#ifdef USE_SK_TX_CHECKSUM + /* Don't handle if Genesis chipset */ + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_IP_CSUM; +#endif +#ifdef USE_SK_RX_CHECKSUM + pAC->RxPort[1].UseRxCsum = SK_TRUE; +#endif + + if (register_netdev(dev)) { + printk(KERN_ERR "SKGE: Could not register device.\n"); + free_netdev(dev); + pAC->dev[1] = pAC->dev[0]; + } else { + + /* Save initial device name */ + strcpy(pNet->InitialDevName, dev->name); + +#ifdef CONFIG_PROC_FS + if (pSkRootDir + && (pProcFile = create_proc_entry(pNet->InitialDevName, + S_IRUGO, pSkRootDir))) { + pProcFile->proc_fops = &sk_proc_fops; + pProcFile->data = dev; + } +#endif + + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); + + printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr); + printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); + } + } + + pAC->Index = sk98lin_boards_found; + sk98lin_max_boards_found = sk98lin_boards_found; + return 0; +} + + /***************************************************************************** * @@ -282,7 +620,7 @@ dev->mem_start = pci_resource_start (pdev, 0); pci_set_master(pdev); - if (pci_request_regions(pdev, pAC->Name) != 0) { + if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) { retval = 2; goto out_disable; } @@ -319,6 +657,315 @@ return retval; } +#ifdef SK_CONFIG_PM +/***************************************************************************** + * + * sk98lin_resume - Resume the the card + * + * Description: + * This function resumes the card into the D0 state + * + * Returns: N/A + * + */ +static int sk98lin_resume(struct pci_dev *pdev) +{ + DEV_NET *pNet; + SK_AC *pAC; + struct net_device *dev = pci_get_drvdata(pdev); + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + /* Set the power state to D0 */ + pci_set_power_state(pdev, 0); + pci_restore_state(pdev, pAC->PciState); + pci_enable_wake(pdev, 3, 0); + pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */ + + + /* Set the adapter power state to D0 */ + SkHWSetDState(pAC, pAC->IoBase, 0); + + /* Reinit the adapter and start the port again */ + SkDrvLeaveDiagMode(pAC); + + netif_device_attach(dev); + + return 0; +} + +/***************************************************************************** + * + * sk98lin_suspend - Suspend the card + * + * Description: + * This function suspends the card into a defined state + * + * Returns: N/A + * + */ +static int sk98lin_suspend(struct pci_dev *pdev, uint32_t state) +{ +DEV_NET *pNet; +SK_AC *pAC; +SK_U16 PciPMControlStatus; +SK_U16 PciPMCapabilities; +SK_MAC_ADDR MacAddr; +struct net_device *dev = pci_get_drvdata(pdev); +int i; + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + netif_device_detach(dev); + + /* Device still busy */ + if(netif_running(dev)) { + /* Maybe we have to close the adapter */ + } + + /* Stop the adapter */ + SkDrvEnterDiagMode(pAC); + + /* read the PM control/status register from the PCI config space */ + SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus); + + /* read the power management capabilities from the config space */ + SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities); + + + /* + * The GE chipset and the first revision of yukon does not + * support power management + */ + if (((pAC->GIni.GIChipId == CHIP_ID_YUKON) && + (pAC->GIni.GIChipRev == 0)) || + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) { + /* Power management not supported */ + printk("Power management not supported\n"); + } else { + /* Enable power management */ + /* Enable WakeUp with Magic Packet */ + /* get MAC address from adapter */ + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + /* virtual address: will be used for data */ + SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]); + } + + /* enable wake up through amd magic packet */ + SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr); + + /* Set port spee to 100MBit */ + SkSetPortSpeed(pAC, pAC->IoBase, SK_LSPEED_100MBPS); + + /* Switch the power state */ + SkHWSwitchPower(pAC, pAC->IoBase, state); + + /* Set the power state + * + * in DState 3 no I/O access to the adapter is possible + * we can only access its PCI Config space through PCI + * BIOS functions + */ + SkHWSetDState(pAC, pAC->IoBase, state); + + pci_enable_wake(pdev, 3, 1); + pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */ + pci_save_state(pdev, pAC->PciState); + + /* Set state */ + pci_set_power_state(pdev, state); + } + return 0; +} + +/****************************************************************************** + * + * SkHWSetDState - Set the desired DState by writing it into the PCI + * config space of the adapter + * + * Context: + * init, pageable + * the adapter must be de-initialized before calling this function + * + * Returns: + * SK_POWER_ERR_OK - everything's fine + */ + +static void SkHWSetDState( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ +SK_DEVICE_POWER_STATE State) /* requested DState */ +{ + SK_U16 PmCtlSts; + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); + + /* reset all DState bits */ + PmCtlSts &= ~(PCI_PM_STATE_D3); + + switch(State) { + case SkDeviceStateD0 : + PmCtlSts |= PCI_PM_STATE_D0; + break; + case SkDeviceStateD1 : + PmCtlSts |= PCI_PM_STATE_D1; + break; + case SkDeviceStateD2 : + PmCtlSts |= PCI_PM_STATE_D2; + break; + case SkDeviceStateD3 : + PmCtlSts |= (PCI_PM_STATE_D3 | PCI_PME_EN); + break; + } + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts); + +} /* SkHWSetDState */ + +/****************************************************************************** + * + * SkHWSwitchPower - Switch the adapter internal power switches according + * to the selected DState + * + * Context: + * init, pageable + * + * Returns: + * SK_POWER_ERR_OK - everything's fine + */ + +static void SkHWSwitchPower( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ +SK_DEVICE_POWER_STATE State) +{ + SK_U8 Byte; + + Byte = PC_VAUX_ENA | PC_VCC_ENA; + + if (State == SkDeviceStateD3) { + /* switch power to Vaux */ + Byte |= PC_VAUX_ON | PC_VCC_OFF; + } + else { + /* switch power to Vcc */ + Byte |= PC_VAUX_OFF | PC_VCC_ON; + } + + SK_OUT8(IoC, B0_POWER_CTRL, Byte); + +} /* SkHWSwitchPower */ + + +/***************************************************************************** +* +* SkSetPortSpeed - switch the link speed of a specific port +* +* Description: +* +* Notes: +* +* Function Parameters: +* pAC - A pointer to our adapter info struct. +* IoC - +* Speed - link speed to switch to +* +* Context: +* IRQL - +* +* Returns: +* +*/ +static int SkSetPortSpeed( +SK_AC *pAC, +SK_IOC IoC, +SK_U8 Speed) +{ + SK_GEPORT *pGePort; + SK_EVPARA EvPara; + + pGePort = &pAC->GIni.GP[0]; + + /* Stop port */ + SkY2PortStop(pAC, pAC->IoBase, 0, SK_STOP_ALL, SK_HARD_RST); + + /* Set port's link speed. */ + if (Speed == SK_LSPEED_100MBPS) { + /* Set port's link mode. */ + pGePort->PLinkSpeed = SK_LSPEED_100MBPS; + pGePort->PLinkModeConf = + pGePort->PLinkMode = SK_LMODE_AUTOBOTH; + } + else { + /* Set port's link mode. */ + pGePort->PLinkSpeed = SK_LSPEED_1000MBPS; + pGePort->PLinkModeConf = + pGePort->PLinkMode = SK_LMODE_FULL; + } + + /* Set port's flow control mode */ + pGePort->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + + /* Set port's Master/Slave param */ + pGePort->PMSMode = SK_MS_MODE_AUTO; + + /* Start the port again so we can switch to the new Link speed */ + SkY2PortStart(pAC, pAC->IoBase, 0); + + return(0); +} + +/****************************************************************************** + * + * SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter + * + * Context: + * init, pageable + * the adapter should be de-initialized before calling this function + * + * Returns: + * nothing + */ + +static void SkEnableWOMagicPacket( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ +SK_MAC_ADDR MacAddr) /* MacAddr expected in magic packet */ +{ + SK_U16 Word; + SK_U32 DWord; + int i; + int HwPortIndex; + + /* use Port 0 as long as we do not have any dual port cards which support WOL */ + HwPortIndex = 0; + DWord = 0; + + for (i = 0; i < 4; i++) { + DWord = DWord << 8; + DWord |= MacAddr.a[3 - i]; + } + + Word = 0; + for (i = 0; i < 2; i++) { + Word = Word << 8; + Word |= MacAddr.a[5 - i]; + } + + /* write MAC address the WOL state machine is waiting for */ + SK_OUT32(IoC, WOL_REG(HwPortIndex, WOL_MAC_ADDR_LO), DWord); + SK_OUT16(IoC, WOL_REG(HwPortIndex, WOL_MAC_ADDR_HI), Word); + + SK_IN16(IoC, WOL_REG(HwPortIndex, WOL_CTRL_STAT), &Word); + + /* enable wake on AMD magic packet */ + Word &= ~(WOL_CTL_DIS_MAGIC_PKT_UNIT | WOL_CTL_DIS_PME_ON_MAGIC_PKT); + Word |= WOL_CTL_ENA_MAGIC_PKT_UNIT | WOL_CTL_ENA_PME_ON_MAGIC_PKT | + WOL_CTL_CLEAR_RESULT; + + SK_OUT16(IoC, WOL_REG(HwPortIndex, WOL_CTRL_STAT), Word); + +} /* SkEnableWOMagicPacket */ +#endif + /***************************************************************************** * @@ -373,13 +1020,9 @@ MODULE_PARM(ConType, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -/* used for interrupt moderation */ MODULE_PARM(IntsPerSec, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i"); MODULE_PARM(Moderation, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(Stats, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); MODULE_PARM(ModerationMask, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(AutoSizing, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); - #ifdef LINK_SPEED_A static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED; @@ -462,8 +1105,99 @@ static int IntsPerSec[SK_MAX_CARD_PARAM]; static char *Moderation[SK_MAX_CARD_PARAM]; static char *ModerationMask[SK_MAX_CARD_PARAM]; -static char *AutoSizing[SK_MAX_CARD_PARAM]; -static char *Stats[SK_MAX_CARD_PARAM]; + + +/***************************************************************************** + * + * sk98lin_remove_device - device deinit function + * + * Description: + * Disable adapter if it is still running, free resources, + * free device struct. + * + * Returns: N/A + */ + +static void sk98lin_remove_device(struct pci_dev *pdev) +{ +DEV_NET *pNet; +SK_AC *pAC; +struct SK_NET_DEVICE *next; +unsigned long Flags; +SK_EVPARA EvPara; +struct net_device *dev = pci_get_drvdata(pdev); + + + /* Device not available. Return. */ + if (!dev) + return; + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + next = pAC->Next; + + netif_stop_queue(dev); + SkGeYellowLED(pAC, pAC->IoBase, 0); + + if(pAC->BoardLevel == SK_INIT_RUN) { + /* board is still alive */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + EvPara.Para32[0] = 0; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + EvPara.Para32[0] = 1; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + SkGeDeInit(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pAC->BoardLevel = SK_INIT_DATA; + /* We do NOT check here, if IRQ was pending, of course*/ + } + + if(pAC->BoardLevel == SK_INIT_IO) { + /* board is still alive */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = SK_INIT_DATA; + } + + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ + unregister_netdev(pAC->dev[1]); + free_netdev(pAC->dev[1]); + } + + FreeResources(dev); + +#ifdef CONFIG_PROC_FS + /* Remove the sk98lin procfs device entries */ + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ + remove_proc_entry(pAC->dev[1]->name, pSkRootDir); + } + remove_proc_entry(pNet->InitialDevName, pSkRootDir); +#endif + + dev->get_stats = NULL; + /* + * otherwise unregister_netdev calls get_stats with + * invalid IO ... :-( + */ + unregister_netdev(dev); + free_netdev(dev); + kfree(pAC); + sk98lin_max_boards_found--; + +#ifdef CONFIG_PROC_FS + /* Remove all Proc entries if last device */ + if (sk98lin_max_boards_found == 0) { + /* clear proc-dir */ + remove_proc_entry(pSkRootDir->name, proc_net); + } +#endif + +} + /***************************************************************************** * @@ -501,7 +1235,9 @@ spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock); spin_lock_init(&pAC->RxPort[i].RxDesRingLock); } + spin_lock_init(&pAC->SlowPathLock); + spin_lock_init(&pAC->SetPutIndexLock); /* for Yukon2 chipsets */ /* level 0 init common modules here */ @@ -525,10 +1261,7 @@ SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString); SK_PNMI_SET_DRIVER_VER(pAC, VerStr); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - /* level 1 init common modules here (HW init) */ - spin_lock_irqsave(&pAC->SlowPathLock, Flags); if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) { printk("sk98lin: HWInit (1) failed.\n"); spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); @@ -542,49 +1275,79 @@ SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO); /* Set chipset type support */ - pAC->ChipsetType = 0; if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) || - (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) { - pAC->ChipsetType = 1; + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) { + pAC->ChipsetType = 1; /* Yukon chipset (descriptor logic) */ + } else if (CHIP_ID_YUKON_2(pAC)) { + pAC->ChipsetType = 2; /* Yukon2 chipset (list logic) */ + } else { + pAC->ChipsetType = 0; /* Genesis chipset (descriptor logic) */ } GetConfiguration(pAC); if (pAC->RlmtNets == 2) { - pAC->GIni.GIPortUsage = SK_MUL_LINK; + pAC->GIni.GIPortUsage = SK_MUL_LINK; } pAC->BoardLevel = SK_INIT_IO; spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - if (pAC->GIni.GIMacsFound == 2) { - Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, pAC->Name, dev); - } else if (pAC->GIni.GIMacsFound == 1) { - Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, - pAC->Name, dev); - } else { - printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n", - pAC->GIni.GIMacsFound); - return -EAGAIN; + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkGePoll; + dev->weight = 64; +#endif + if (pAC->GIni.GIMacsFound == 2) { + Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev); + } else if (pAC->GIni.GIMacsFound == 1) { + Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, dev->name, dev); + } else { + printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n", + pAC->GIni.GIMacsFound); + return -EAGAIN; + } + } + else { + Ret = request_irq(dev->irq, SkY2Isr, SA_SHIRQ, dev->name, dev); +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkY2Poll; + dev->weight = 64; +#endif } if (Ret) { printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n", - dev->irq); + dev->irq); return -EAGAIN; } pAC->AllocFlag |= SK_ALLOC_IRQ; - /* Alloc memory for this board (Mem for RxD/TxD) : */ - if(!BoardAllocMem(pAC)) { - printk("No memory for descriptor rings.\n"); - return(-EAGAIN); + /* + ** Alloc descriptor/LETable memory for this board (both RxD/TxD) + */ + if (CHIP_ID_YUKON_2(pAC)) { + if (!SkY2AllocateResources(pAC)) { + printk("No memory for Yukon2 settings\n"); + return(-EAGAIN); + } + } else { + if(!BoardAllocMem(pAC)) { + printk("No memory for descriptor rings.\n"); + return(-EAGAIN); + } } +#ifdef SK_USE_CSUM SkCsSetReceiveFlags(pAC, SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP, &pAC->CsOfs1, &pAC->CsOfs2, 0); pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1; +#endif + /* + ** Function BoardInitMem() for Yukon dependent settings... + */ BoardInitMem(pAC); /* tschilling: New common function with minimum size check. */ DualNet = SK_FALSE; @@ -696,6 +1459,12 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("BoardFreeMem\n")); + + if (CHIP_ID_YUKON_2(pAC)) { + SkY2FreeResources(pAC); + return; + } + #if (BITS_PER_LONG == 32) AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; #else @@ -714,7 +1483,7 @@ * BoardInitMem - initiate the descriptor rings * * Description: - * This function sets the descriptor rings up in memory. + * This function sets the descriptor rings or LETables up in memory. * The adapter is initialized with the descriptor start addresses. * * Returns: N/A @@ -729,34 +1498,37 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("BoardInitMem\n")); - RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; - pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize; - TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; - pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; + if (!pAC->GIni.GIYukon2) { + RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize; + TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; - for (i=0; iGIni.GIMacsFound; i++) { - SetupRing( - pAC, - pAC->TxPort[i][0].pTxDescrRing, - pAC->TxPort[i][0].VTxDescrRing, - (RXD**)&pAC->TxPort[i][0].pTxdRingHead, - (RXD**)&pAC->TxPort[i][0].pTxdRingTail, - (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, - &pAC->TxPort[i][0].TxdRingFree, - SK_TRUE); - SetupRing( - pAC, - pAC->RxPort[i].pRxDescrRing, - pAC->RxPort[i].VRxDescrRing, - &pAC->RxPort[i].pRxdRingHead, - &pAC->RxPort[i].pRxdRingTail, - &pAC->RxPort[i].pRxdRingPrev, - &pAC->RxPort[i].RxdRingFree, - SK_FALSE); + for (i=0; iGIni.GIMacsFound; i++) { + SetupRing( + pAC, + pAC->TxPort[i][0].pTxDescrRing, + pAC->TxPort[i][0].VTxDescrRing, + (RXD**)&pAC->TxPort[i][0].pTxdRingHead, + (RXD**)&pAC->TxPort[i][0].pTxdRingTail, + (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, + &pAC->TxPort[i][0].TxdRingFree, + &pAC->TxPort[i][0].TxdRingPrevFree, + SK_TRUE); + SetupRing( + pAC, + pAC->RxPort[i].pRxDescrRing, + pAC->RxPort[i].VRxDescrRing, + &pAC->RxPort[i].pRxdRingHead, + &pAC->RxPort[i].pRxdRingTail, + &pAC->RxPort[i].pRxdRingPrev, + &pAC->RxPort[i].RxdRingFree, + &pAC->RxPort[i].RxdRingFree, + SK_FALSE); + } } } /* BoardInitMem */ - /***************************************************************************** * * SetupRing - create one descriptor ring @@ -776,6 +1548,7 @@ RXD **ppRingTail, /* address where the tail should be written */ RXD **ppRingPrev, /* address where the tail should be written */ int *pRingFree, /* address where the # of free descr. goes */ +int *pRingPrevFree, /* address where the # of free descr. goes */ SK_BOOL IsTx) /* flag: is this a tx ring */ { int i; /* loop counter */ @@ -818,11 +1591,12 @@ } pPrevDescr->pNextRxd = (RXD*) pMemArea; pPrevDescr->VNextRxd = VMemArea; - pDescr = (RXD*) pMemArea; - *ppRingHead = (RXD*) pMemArea; - *ppRingTail = *ppRingHead; - *ppRingPrev = pPrevDescr; - *pRingFree = DescrNum; + pDescr = (RXD*) pMemArea; + *ppRingHead = (RXD*) pMemArea; + *ppRingTail = *ppRingHead; + *ppRingPrev = pPrevDescr; + *pRingFree = DescrNum; + *pRingPrevFree = DescrNum; } /* SetupRing */ @@ -898,6 +1672,24 @@ return SkIsrRetNone; } +#ifdef CONFIG_SK98LIN_NAPI + if (netif_rx_schedule_prep(dev)) { + pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + __netif_rx_schedule(dev); + } + +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IS_XA1_F) { + CLEAR_TX_IRQ(0, TX_PRIO_LOW); + } + if (IntSrc & IS_XA2_F) { + CLEAR_TX_IRQ(1, TX_PRIO_LOW); + } +#endif + + +#else while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { #if 0 /* software irq currently not used */ if (IntSrc & IS_IRQ_SW) { @@ -911,6 +1703,7 @@ SK_DBGCAT_DRV_INT_SRC, ("EOF RX1 IRQ\n")); ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + CLEAR_AND_START_RX(0); SK_PNMI_CNT_RX_INTR(pAC, 0); } if (IntSrc & IS_R2_F) { @@ -918,6 +1711,7 @@ SK_DBGCAT_DRV_INT_SRC, ("EOF RX2 IRQ\n")); ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); + CLEAR_AND_START_RX(1); SK_PNMI_CNT_RX_INTR(pAC, 1); } #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ @@ -925,6 +1719,7 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF AS TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_LOW); SK_PNMI_CNT_TX_INTR(pAC, 0); spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); @@ -934,6 +1729,7 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF AS TX2 IRQ\n")); + CLEAR_TX_IRQ(1, TX_PRIO_LOW); SK_PNMI_CNT_TX_INTR(pAC, 1); spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]); @@ -944,38 +1740,28 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF SY TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_HIGH); SK_PNMI_CNT_TX_INTR(pAC, 1); spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); - ClearTxIrq(pAC, 0, TX_PRIO_HIGH); } if (IntSrc & IS_XS2_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF SY TX2 IRQ\n")); + CLEAR_TX_IRQ(1, TX_PRIO_HIGH); SK_PNMI_CNT_TX_INTR(pAC, 1); spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH); spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); - ClearTxIrq(pAC, 1, TX_PRIO_HIGH); } #endif #endif - /* do all IO at once */ - if (IntSrc & IS_R1_F) - ClearAndStartRx(pAC, 0); - if (IntSrc & IS_R2_F) - ClearAndStartRx(pAC, 1); -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ - if (IntSrc & IS_XA1_F) - ClearTxIrq(pAC, 0, TX_PRIO_LOW); - if (IntSrc & IS_XA2_F) - ClearTxIrq(pAC, 1, TX_PRIO_LOW); -#endif SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); } /* while (IntSrc & IRQ_MASK != 0) */ +#endif IntSrc &= pAC->GIni.GIValIrqMask; if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { @@ -989,18 +1775,12 @@ SkEventDispatcher(pAC, pAC->IoBase); spin_unlock(&pAC->SlowPathLock); } - /* - * do it all again is case we cleared an interrupt that - * came in after handling the ring (OUTs may be delayed - * in hardware buffers, but are through after IN) - * - * rroesler: has been commented out and shifted to - * SkGeDrvEvent(), because it is timer - * guarded now - * + +#ifndef CONFIG_SK98LIN_NAPI + /* Handle interrupts */ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); - */ +#endif if (pAC->CheckQueue) { pAC->CheckQueue = SK_FALSE; @@ -1047,6 +1827,21 @@ return SkIsrRetNone; } +#ifdef CONFIG_SK98LIN_NAPI + if (netif_rx_schedule_prep(dev)) { + // CLEAR_AND_START_RX(0); + // CLEAR_TX_IRQ(0, TX_PRIO_LOW); + pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + __netif_rx_schedule(dev); + } + +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IS_XA1_F) { + CLEAR_TX_IRQ(0, TX_PRIO_LOW); + } +#endif +#else while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { #if 0 /* software irq currently not used */ if (IntSrc & IS_IRQ_SW) { @@ -1060,6 +1855,7 @@ SK_DBGCAT_DRV_INT_SRC, ("EOF RX1 IRQ\n")); ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + CLEAR_AND_START_RX(0); SK_PNMI_CNT_RX_INTR(pAC, 0); } #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ @@ -1067,6 +1863,7 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF AS TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_LOW); SK_PNMI_CNT_TX_INTR(pAC, 0); spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); @@ -1077,24 +1874,18 @@ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF SY TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_HIGH); SK_PNMI_CNT_TX_INTR(pAC, 0); spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); - ClearTxIrq(pAC, 0, TX_PRIO_HIGH); } #endif #endif - /* do all IO at once */ - if (IntSrc & IS_R1_F) - ClearAndStartRx(pAC, 0); -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ - if (IntSrc & IS_XA1_F) - ClearTxIrq(pAC, 0, TX_PRIO_LOW); -#endif SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); } /* while (IntSrc & IRQ_MASK != 0) */ +#endif IntSrc &= pAC->GIni.GIValIrqMask; if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { @@ -1108,17 +1899,10 @@ SkEventDispatcher(pAC, pAC->IoBase); spin_unlock(&pAC->SlowPathLock); } - /* - * do it all again is case we cleared an interrupt that - * came in after handling the ring (OUTs may be delayed - * in hardware buffers, but are through after IN) - * - * rroesler: has been commented out and shifted to - * SkGeDrvEvent(), because it is timer - * guarded now - * + +#ifndef CONFIG_SK98LIN_NAPI ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); - */ +#endif /* IRQ is processed - Enable IRQs again*/ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); @@ -1126,7 +1910,6 @@ return SkIsrRetHandled; } /* SkGeIsrOnePort */ - /**************************************************************************** * * SkGeOpen - handle start of initialized adapter @@ -1144,27 +1927,22 @@ * != 0 on error */ static int SkGeOpen( -struct SK_NET_DEVICE *dev) +struct SK_NET_DEVICE *dev) /* the device that is to be opened */ { - DEV_NET *pNet; - SK_AC *pAC; - unsigned long Flags; /* for spin lock */ - int i; - SK_EVPARA EvPara; /* an event parameter union */ + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + unsigned long Flags; /* for the spin locks */ + int CurrMac; /* loop ctr for ports */ + SK_EVPARA EvPara; /* event parameter union */ - pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC)); -#ifdef SK_DIAG_SUPPORT if (pAC->DiagModeActive == DIAG_ACTIVE) { if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) { return (-1); /* still in use by diag; deny actions */ } } -#endif if (!try_module_get(THIS_MODULE)) { return (-1); /* increase of usage count not possible */ @@ -1206,18 +1984,31 @@ pAC->BoardLevel = SK_INIT_RUN; } - for (i=0; iGIni.GIMacsFound; i++) { - /* Enable transmit descriptor polling. */ - SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); - FillRxRing(pAC, &pAC->RxPort[i]); + for (CurrMac=0; CurrMacGIni.GIMacsFound; CurrMac++) { + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStart(pAC, pAC->IoBase, CurrMac); + } else { + /* Enable transmit descriptor polling. */ + SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[CurrMac]); + SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr); + } } - SkGeYellowLED(pAC, pAC->IoBase, 1); - StartDrvCleanupTimer(pAC); + SkGeYellowLED(pAC, pAC->IoBase, 1); SkDimEnableModerationIfNeeded(pAC); - SkDimDisplayModerationSettings(pAC); - pAC->GIni.GIValIrqMask &= IRQ_MASK; + if (!CHIP_ID_YUKON_2(pAC)) { + /* + ** Has been setup already at SkGeInit(SK_INIT_IO), + ** but additional masking added for Genesis & Yukon + ** chipsets -> modify it... + */ + pAC->GIni.GIValIrqMask &= IRQ_MASK; +#ifndef USE_TX_COMPLETE + pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS); +#endif + } /* enable Interrupts */ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); @@ -1265,24 +2056,22 @@ * error code - on error */ static int SkGeClose( -struct SK_NET_DEVICE *dev) +struct SK_NET_DEVICE *dev) /* the device that is to be closed */ { - DEV_NET *pNet; - DEV_NET *newPtrNet; - SK_AC *pAC; - - unsigned long Flags; /* for spin lock */ - int i; - int PortIdx; - SK_EVPARA EvPara; - + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + DEV_NET *newPtrNet; + unsigned long Flags; /* for the spin locks */ + int CurrMac; /* loop ctr for the current MAC */ + int PortIdx; + SK_EVPARA EvPara; +#ifdef CONFIG_SK98LIN_NAPI + int WorkToDo = 1; /* min(*budget, dev->quota); */ + int WorkDone = 0; +#endif SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC)); - pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; - -#ifdef SK_DIAG_SUPPORT if (pAC->DiagModeActive == DIAG_ACTIVE) { if (pAC->DiagFlowCtrl == SK_FALSE) { module_put(THIS_MODULE); @@ -1302,7 +2091,6 @@ pAC->DiagFlowCtrl = SK_FALSE; } } -#endif netif_stop_queue(dev); @@ -1311,8 +2099,6 @@ else PortIdx = pNet->NetNr; - StopDrvCleanupTimer(pAC); - /* * Clear multicast table, promiscuous mode .... */ @@ -1330,8 +2116,14 @@ SkEventDispatcher(pAC, pAC->IoBase); SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* stop the hardware */ - SkGeDeInit(pAC, pAC->IoBase); - pAC->BoardLevel = SK_INIT_DATA; + /* SkGeDeInit(pAC, pAC->IoBase); */ + /* pAC->BoardLevel = SK_INIT_DATA; */ + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, pAC->IoBase, 0, SK_STOP_ALL, SK_HARD_RST); + } + else { + SkGeStopPort(pAC, pAC->IoBase, 0, SK_STOP_ALL, SK_HARD_RST); + } spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); } else { @@ -1346,24 +2138,52 @@ /* Stop port */ spin_lock_irqsave(&pAC->TxPort[pNet->PortNr] [TX_PRIO_LOW].TxDesRingLock, Flags); - SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, - SK_STOP_ALL, SK_HARD_RST); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, + SK_STOP_ALL, SK_HARD_RST); + } + else { + SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, + SK_STOP_ALL, SK_HARD_RST); + } spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr] [TX_PRIO_LOW].TxDesRingLock, Flags); } if (pAC->RlmtNets == 1) { /* clear all descriptor rings */ - for (i=0; iGIni.GIMacsFound; i++) { - ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); - ClearRxRing(pAC, &pAC->RxPort[i]); - ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]); + for (CurrMac=0; CurrMacGIni.GIMacsFound; CurrMac++) { + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC,&pAC->RxPort[CurrMac], + SK_TRUE,&WorkDone,WorkToDo); +#else + ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE); +#endif + ClearRxRing(pAC, &pAC->RxPort[CurrMac]); + ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]); + } else { + SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac); + SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac); + } } } else { /* clear port descriptor rings */ - ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); - ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); - ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]); + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); +#endif + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]); + } + else { + SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr); + SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr); + } } SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, @@ -1434,9 +2254,11 @@ } /* Transmitter out of resources? */ +#ifdef USE_TX_COMPLETE if (Rc <= 0) { netif_stop_queue(dev); } +#endif /* If not taken, give buffer ownership back to the * queueing layer. @@ -1448,6 +2270,53 @@ return (0); } /* SkGeXmit */ +#ifdef CONFIG_SK98LIN_NAPI +/***************************************************************************** + * + * SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets + * + * Description: + * Called by the Linux system in case NAPI polling is activated + * + * Returns: + * The number of work data still to be handled + */ +static int SkGePoll(struct net_device *dev, int *budget) +{ +SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */ +int WorkToDo = min(*budget, dev->quota); +int WorkDone = 0; + + if (pAC->dev[0] != pAC->dev[1]) { +#ifdef USE_TX_COMPLETE + spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); +#endif + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo); + } +#ifdef USE_TX_COMPLETE + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); +#endif + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo); + + *budget -= WorkDone; + dev->quota -= WorkDone; + + if(WorkDone < WorkToDo) { + netif_rx_complete(dev); + /* enable interrupts again */ + pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS); +#ifndef USE_TX_COMPLETE + pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS); +#endif + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + } + return (WorkDone >= WorkToDo); +} /* SkGePoll */ +#endif /***************************************************************************** * @@ -1472,7 +2341,7 @@ * < 0 - on failure: other problems ( -> return failure to upper layers) */ static int XmitFrame( -SK_AC *pAC, /* pointer to adapter context */ +SK_AC *pAC, /* pointer to adapter context */ TX_PORT *pTxPort, /* pointer to struct of port to send to */ struct sk_buff *pMessage) /* pointer to send-message */ { @@ -1488,11 +2357,14 @@ spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); #ifndef USE_TX_COMPLETE - FreeTxDescriptors(pAC, pTxPort); + if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6) { + FreeTxDescriptors(pAC, pTxPort); + pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree; + } #endif if (pTxPort->TxdRingFree == 0) { /* - ** no enough free descriptors in ring at the moment. + ** not enough free descriptors in ring at the moment. ** Maybe free'ing some old one help? */ FreeTxDescriptors(pAC, pTxPort); @@ -1578,7 +2450,7 @@ BMU_IRQ_EOF | #endif pMessage->len; - } else { + } else { pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK | BMU_SW | BMU_EOF | #ifdef USE_TX_COMPLETE @@ -1998,33 +2870,40 @@ * Returns: N/A */ static void ReceiveIrq( - SK_AC *pAC, /* pointer to adapter context */ - RX_PORT *pRxPort, /* pointer to receive port struct */ - SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */ -{ -RXD *pRxd; /* pointer to receive descriptors */ -SK_U32 Control; /* control field of descriptor */ -struct sk_buff *pMsg; /* pointer to message holding frame */ -struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */ -int FrameLength; /* total length of received frame */ -int IpFrameLength; -SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */ -SK_EVPARA EvPara; /* an event parameter union */ -unsigned long Flags; /* for spin lock */ -int PortIndex = pRxPort->PortIndex; -unsigned int Offset; -unsigned int NumBytes; -unsigned int ForRlmt; -SK_BOOL IsBc; -SK_BOOL IsMc; -SK_BOOL IsBadFrame; /* Bad frame */ - -SK_U32 FrameStat; -unsigned short Csum1; -unsigned short Csum2; -unsigned short Type; -int Result; -SK_U64 PhysAddr; +#ifdef CONFIG_SK98LIN_NAPI +SK_AC *pAC, /* pointer to adapter context */ +RX_PORT *pRxPort, /* pointer to receive port struct */ +SK_BOOL SlowPathLock, /* indicates if SlowPathLock is needed */ +int *WorkDone, +int WorkToDo) +#else +SK_AC *pAC, /* pointer to adapter context */ +RX_PORT *pRxPort, /* pointer to receive port struct */ +SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */ +#endif +{ + RXD *pRxd; /* pointer to receive descriptors */ + struct sk_buff *pMsg; /* pointer to message holding frame */ + struct sk_buff *pNewMsg; /* pointer to new message for frame copy */ + SK_MBUF *pRlmtMbuf; /* ptr to buffer for giving frame to RLMT */ + SK_EVPARA EvPara; /* an event parameter union */ + SK_U32 Control; /* control field of descriptor */ + unsigned long Flags; /* for spin lock handling */ + int PortIndex = pRxPort->PortIndex; + int FrameLength; /* total length of received frame */ + int IpFrameLength; /* IP length of the received frame */ + unsigned int Offset; + unsigned int NumBytes; + unsigned int RlmtNotifier; + SK_BOOL IsBc; /* we received a broadcast packet */ + SK_BOOL IsMc; /* we received a multicast packet */ + SK_BOOL IsBadFrame; /* the frame received is bad! */ + SK_U32 FrameStat; + unsigned short Csum1; + unsigned short Csum2; + unsigned short Type; + int Result; + SK_U64 PhysAddr; rx_start: /* do forever; exit if BMU_OWN found */ @@ -2046,6 +2925,13 @@ Control = pRxd->RBControl; +#ifdef CONFIG_SK98LIN_NAPI + if (*WorkDone >= WorkToDo) { + break; + } + (*WorkDone)++; +#endif + /* check if this descriptor is ready */ if ((Control & BMU_OWN) != 0) { /* this descriptor is not yet ready */ @@ -2054,7 +2940,6 @@ FillRxRing(pAC, pRxPort); return; } - pAC->DynIrqModInfo.NbrProcessedDescr++; /* get length of frame and check it */ FrameLength = Control & BMU_BBC; @@ -2073,8 +2958,8 @@ FrameStat = pRxd->FrameStat; /* check for frame length mismatch */ -#define XMR_FS_LEN_SHIFT 18 -#define GMR_FS_LEN_SHIFT 16 +#define XMR_FS_LEN_SHIFT 18 +#define GMR_FS_LEN_SHIFT 16 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, @@ -2084,8 +2969,7 @@ (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT))); goto rx_failed; } - } - else { + } else { if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, @@ -2128,6 +3012,12 @@ "Control: %x\nRxStat: %x\n", Control, FrameStat)); + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_dma_sync_single_for_cpu(pAC->PciDev, + (dma_addr_t) PhysAddr, + FrameLength, + PCI_DMA_FROMDEVICE); ReQueueRxBuffer(pAC, pRxPort, pMsg, pRxd->VDataHigh, pRxd->VDataLow); @@ -2147,29 +3037,23 @@ skb_put(pNewMsg, FrameLength); PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_dma_sync_single_for_device(pAC->PciDev, + (dma_addr_t) PhysAddr, + FrameLength, + PCI_DMA_FROMDEVICE); - pci_dma_sync_single_for_cpu(pAC->PciDev, - (dma_addr_t) PhysAddr, - FrameLength, - PCI_DMA_FROMDEVICE); eth_copy_and_sum(pNewMsg, pMsg->data, FrameLength, 0); - pci_dma_sync_single_for_device(pAC->PciDev, - (dma_addr_t) PhysAddr, - FrameLength, - PCI_DMA_FROMDEVICE); ReQueueRxBuffer(pAC, pRxPort, pMsg, pRxd->VDataHigh, pRxd->VDataLow); pMsg = pNewMsg; - } - else { + } else { /* * if large frame, or SKB allocation failed, pass * the SKB directly to the networking */ - PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; PhysAddr |= (SK_U64) pRxd->VDataLow; @@ -2178,119 +3062,75 @@ PhysAddr, pAC->RxBufSize - 2, PCI_DMA_FROMDEVICE); + skb_put(pMsg, FrameLength); /* set message len */ + pMsg->ip_summed = CHECKSUM_NONE; /* initial default */ - /* set length in message */ - skb_put(pMsg, FrameLength); - /* hardware checksum */ - Type = ntohs(*((short*)&pMsg->data[12])); - -#ifdef USE_SK_RX_CHECKSUM - if (Type == 0x800) { - Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff); - Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff); - IpFrameLength = (int) ntohs((unsigned short) - ((unsigned short *) pMsg->data)[8]); - - /* - * Test: If frame is padded, a check is not possible! - * Frame not padded? Length difference must be 14 (0xe)! - */ - if ((FrameLength - IpFrameLength) != 0xe) { - /* Frame padded => TCP offload not possible! */ - pMsg->ip_summed = CHECKSUM_NONE; - } else { - /* Frame not padded => TCP offload! */ - if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) && - (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) || - (pAC->ChipsetType)) { - Result = SkCsGetReceiveInfo(pAC, - &pMsg->data[14], - Csum1, Csum2, pRxPort->PortIndex); - if (Result == - SKCS_STATUS_IP_FRAGMENT || - Result == - SKCS_STATUS_IP_CSUM_OK || - Result == - SKCS_STATUS_TCP_CSUM_OK || - Result == - SKCS_STATUS_UDP_CSUM_OK) { - pMsg->ip_summed = - CHECKSUM_UNNECESSARY; - } - else if (Result == - SKCS_STATUS_TCP_CSUM_ERROR || - Result == - SKCS_STATUS_UDP_CSUM_ERROR || - Result == - SKCS_STATUS_IP_CSUM_ERROR_UDP || - Result == - SKCS_STATUS_IP_CSUM_ERROR_TCP || - Result == - SKCS_STATUS_IP_CSUM_ERROR ) { - /* HW Checksum error */ - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, - ("skge: CRC error. Frame dropped!\n")); - goto rx_failed; - } else { - pMsg->ip_summed = - CHECKSUM_NONE; - } - }/* checksumControl calculation valid */ - } /* Frame length check */ - } /* IP frame */ -#else - pMsg->ip_summed = CHECKSUM_NONE; -#endif + if (pRxPort->UseRxCsum) { + Type = ntohs(*((short*)&pMsg->data[12])); + if (Type == 0x800) { + IpFrameLength = (int) ntohs((unsigned short) + ((unsigned short *) pMsg->data)[8]); + if ((FrameLength - IpFrameLength) == 0xe) { + Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff); + Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff); + if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) && + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) || + (pAC->ChipsetType)) { + Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14], + Csum1, Csum2, PortIndex); + if ((Result == SKCS_STATUS_IP_FRAGMENT) || + (Result == SKCS_STATUS_IP_CSUM_OK) || + (Result == SKCS_STATUS_TCP_CSUM_OK) || + (Result == SKCS_STATUS_UDP_CSUM_OK)) { + pMsg->ip_summed = CHECKSUM_UNNECESSARY; + } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) || + (Result == SKCS_STATUS_UDP_CSUM_ERROR) || + (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) || + (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) || + (Result == SKCS_STATUS_IP_CSUM_ERROR)) { + /* HW Checksum error */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: CRC error. Frame dropped!\n")); + goto rx_failed; + } else { + pMsg->ip_summed = CHECKSUM_NONE; + } + }/* checksumControl calculation valid */ + } /* Frame length check */ + } /* IP frame */ + } /* pRxPort->UseRxCsum */ } /* frame > SK_COPY_TRESHOLD */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V")); - ForRlmt = SK_RLMT_RX_PROTOCOL; -#if 0 - IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC; -#endif + RlmtNotifier = SK_RLMT_RX_PROTOCOL; SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength, - IsBc, &Offset, &NumBytes); + IsBc, &Offset, &NumBytes); if (NumBytes != 0) { -#if 0 - IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC; -#endif - SK_RLMT_LOOKAHEAD(pAC, PortIndex, - &pMsg->data[Offset], - IsBc, IsMc, &ForRlmt); + SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset], + IsBc,IsMc,&RlmtNotifier); } - if (ForRlmt == SK_RLMT_RX_PROTOCOL) { - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W")); + if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W")); /* send up only frames from active port */ - if ((PortIndex == pAC->ActivePort) || - (pAC->RlmtNets == 2)) { - /* frame for upper layer */ + if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U")); #ifdef xDEBUG DumpMsg(pMsg, "Rx"); #endif - SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC, - FrameLength, pRxPort->PortIndex); - - pMsg->dev = pAC->dev[pRxPort->PortIndex]; - pMsg->protocol = eth_type_trans(pMsg, - pAC->dev[pRxPort->PortIndex]); - netif_rx(pMsg); - pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; - } - else { - /* drop frame */ + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex); + pMsg->dev = pAC->dev[PortIndex]; + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]); + netif_rx(pMsg); /* frame for upper layer */ + pAC->dev[PortIndex]->last_rx = jiffies; + } else { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, - ("D")); - DEV_KFREE_SKB(pMsg); + SK_DBGCAT_DRV_RX_PROGRESS,("D")); + DEV_KFREE_SKB(pMsg); /* drop frame */ } - - } /* if not for rlmt */ - else { - /* packet for rlmt */ + } else { /* packet for RLMT stack */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, ("R")); + SK_DBGCAT_DRV_RX_PROGRESS,("R")); pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC, pAC->IoBase, FrameLength); if (pRlmtMbuf != NULL) { @@ -2318,32 +3158,22 @@ } SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, - ("Q")); + SK_DBGCAT_DRV_RX_PROGRESS,("Q")); } - if ((pAC->dev[pRxPort->PortIndex]->flags & - (IFF_PROMISC | IFF_ALLMULTI)) != 0 || - (ForRlmt & SK_RLMT_RX_PROTOCOL) == - SK_RLMT_RX_PROTOCOL) { - pMsg->dev = pAC->dev[pRxPort->PortIndex]; - pMsg->protocol = eth_type_trans(pMsg, - pAC->dev[pRxPort->PortIndex]); + if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) || + (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) { + pMsg->dev = pAC->dev[PortIndex]; + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]); netif_rx(pMsg); - pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; - } - else { + pAC->dev[PortIndex]->last_rx = jiffies; + } else { DEV_KFREE_SKB(pMsg); } - - } /* if packet for rlmt */ + } /* if packet for RLMT stack */ } /* for ... scanning the RXD ring */ /* RXD ring is empty -> fill and restart */ FillRxRing(pAC, pRxPort); - /* do not start if called from Close */ - if (pAC->BoardLevel > SK_INIT_DATA) { - ClearAndStartRx(pAC, PortIndex); - } return; rx_failed: @@ -2367,49 +3197,6 @@ } /* ReceiveIrq */ - -/***************************************************************************** - * - * ClearAndStartRx - give a start receive command to BMU, clear IRQ - * - * Description: - * This function sends a start command and a clear interrupt - * command for one receive queue to the BMU. - * - * Returns: N/A - * none - */ -static void ClearAndStartRx( -SK_AC *pAC, /* pointer to the adapter context */ -int PortIndex) /* index of the receive port (XMAC) */ -{ - SK_OUT8(pAC->IoBase, - RxQueueAddr[PortIndex]+Q_CSR, - CSR_START | CSR_IRQ_CL_F); -} /* ClearAndStartRx */ - - -/***************************************************************************** - * - * ClearTxIrq - give a clear transmit IRQ command to BMU - * - * Description: - * This function sends a clear tx IRQ command for one - * transmit queue to the BMU. - * - * Returns: N/A - */ -static void ClearTxIrq( -SK_AC *pAC, /* pointer to the adapter context */ -int PortIndex, /* index of the transmit port (XMAC) */ -int Prio) /* priority or normal queue */ -{ - SK_OUT8(pAC->IoBase, - TxQueueAddr[PortIndex][Prio]+Q_CSR, - CSR_IRQ_CL_F); -} /* ClearTxIrq */ - - /***************************************************************************** * * ClearRxRing - remove all buffers from the receive ring @@ -2623,6 +3410,10 @@ unsigned long Flags; int i; SK_EVPARA EvPara; +#ifdef CONFIG_SK98LIN_NAPI +int WorkToDo = 1; // min(*budget, dev->quota); +int WorkDone = 0; +#endif SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeChangeMtu starts now...\n")); @@ -2638,7 +3429,6 @@ return -EINVAL; } -#ifdef SK_DIAG_SUPPORT if (pAC->DiagModeActive == DIAG_ACTIVE) { if (pAC->DiagFlowCtrl == SK_FALSE) { return -1; /* still in use, deny any actions of MTU */ @@ -2646,7 +3436,6 @@ pAC->DiagFlowCtrl = SK_FALSE; } } -#endif pNet->Mtu = NewMtu; pOtherNet = (DEV_NET*)pAC->dev[1 - pNet->NetNr]->priv; @@ -2655,6 +3444,9 @@ } pAC->RxBufSize = NewMtu + 32; + while (pAC->RxBufSize % 8) { /* RxBufSize must be a multiple of 8 */ + pAC->RxBufSize = pAC->RxBufSize + 1; + } dev->mtu = NewMtu; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, @@ -2738,7 +3530,6 @@ ** enable/disable hardware support for long frames */ if (NewMtu > 1500) { -// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */ pAC->GIni.GIPortUsage = SK_JUMBO_LINK; } else { if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { @@ -2755,9 +3546,8 @@ SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO); SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO); SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO); - + /* - ** tschilling: ** Speed and others are set back to default in level 1 init! */ GetConfiguration(pAC); @@ -2771,23 +3561,35 @@ SkTimerInit(pAC, pAC->IoBase, SK_INIT_RUN); /* - ** clear and reinit the rx rings here + ** clear and reinit the rx rings here, because of new MTU size */ for (i=0; iGIni.GIMacsFound; i++) { - ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); - ClearRxRing(pAC, &pAC->RxPort[i]); - FillRxRing(pAC, &pAC->RxPort[i]); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2FreeRxBuffers(pAC, pAC->IoBase, i); + SkY2FreeTxBuffers(pAC, pAC->IoBase, i); + SkY2AllocateRxBuffers(pAC, pAC->IoBase, i); + SkY2RestartStatusUnit(pAC); + SkY2PortStart(pAC, pAC->IoBase, i); + } else { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); +#endif + ClearRxRing(pAC, &pAC->RxPort[i]); + FillRxRing(pAC, &pAC->RxPort[i]); - /* - ** Enable transmit descriptor polling - */ - SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); - FillRxRing(pAC, &pAC->RxPort[i]); - }; + /* + ** Enable transmit descriptor polling + */ + SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[i]); + } + } SkGeYellowLED(pAC, pAC->IoBase, 1); SkDimEnableModerationIfNeeded(pAC); - SkDimDisplayModerationSettings(pAC); netif_start_queue(pAC->dev[pNet->PortNr]); for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) { @@ -2857,42 +3659,38 @@ { DEV_NET *pNet = (DEV_NET*) dev->priv; SK_AC *pAC = pNet->pAC; -SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */ -SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */ -SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */ -unsigned int Size; /* size of pnmi struct */ +SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */ +SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */ +SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */ +unsigned int Size; /* size of pnmi struct */ unsigned long Flags; /* for spin lock */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeStats starts now...\n")); pPnmiStruct = &pAC->PnmiStruct; -#ifdef SK_DIAG_SUPPORT - if ((pAC->DiagModeActive == DIAG_NOTACTIVE) && - (pAC->BoardLevel == SK_INIT_RUN)) { -#endif - SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA)); - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - Size = SK_PNMI_STRUCT_SIZE; - SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); -#ifdef SK_DIAG_SUPPORT + if ((pAC->DiagModeActive == DIAG_NOTACTIVE) && + (pAC->BoardLevel == SK_INIT_RUN)) { + SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA)); + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + Size = SK_PNMI_STRUCT_SIZE; + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); } -#endif - pPnmiStat = &pPnmiStruct->Stat[0]; - pPnmiConf = &pPnmiStruct->Conf[0]; + pPnmiStat = &pPnmiStruct->Stat[0]; + pPnmiConf = &pPnmiStruct->Conf[0]; pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF; pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF; pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts; pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts; - if (pNet->Mtu <= 1500) { - pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF; - } else { - pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts - - pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF); + if (pNet->Mtu <= 1500) { + pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF; + } else { + pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF); } @@ -2939,28 +3737,27 @@ */ static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd) { -DEV_NET *pNet; -SK_AC *pAC; -void *pMemBuf; -struct pci_dev *pdev = NULL; -SK_GE_IOCTL Ioctl; -unsigned int Err = 0; -int Size = 0; -int Ret = 0; -unsigned int Length = 0; -int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32); + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + struct pci_dev *pdev = NULL; + void *pMemBuf; + SK_GE_IOCTL Ioctl; + unsigned int Err = 0; + unsigned int Length = 0; + int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32); + int Size = 0; + int Ret = 0; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeIoctl starts now...\n")); - pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; - if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) { return -EFAULT; } switch(cmd) { + case SIOCETHTOOL: + return SkEthIoctl(dev, rq); case SK_IOCTL_SETMIB: case SK_IOCTL_PRESETMIB: if (!capable(CAP_NET_ADMIN)) return -EPERM; @@ -3009,8 +3806,7 @@ fault_gen: kfree(pMemBuf); /* cleanup everything */ break; -#ifdef SK_DIAG_SUPPORT - case SK_IOCTL_DIAG: + case SK_IOCTL_DIAG: if (!capable(CAP_NET_ADMIN)) return -EPERM; if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) { Length = Ioctl.Len; @@ -3047,7 +3843,6 @@ fault_diag: kfree(pMemBuf); /* cleanup everything */ break; -#endif default: Err = -EOPNOTSUPP; } @@ -3127,17 +3922,18 @@ SK_I32 Port; /* preferred port */ SK_BOOL AutoSet; SK_BOOL DupSet; -int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */ -int AutoNeg = 1; /* autoneg off (0) or on (1) */ -int DuplexCap = 0; /* 0=both,1=full,2=half */ -int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */ -int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */ - -SK_BOOL IsConTypeDefined = SK_TRUE; -SK_BOOL IsLinkSpeedDefined = SK_TRUE; -SK_BOOL IsFlowCtrlDefined = SK_TRUE; -SK_BOOL IsRoleDefined = SK_TRUE; -SK_BOOL IsModeDefined = SK_TRUE; +int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */ +int AutoNeg = 1; /* autoneg off (0) or on (1) */ +int DuplexCap = 0; /* 0=both,1=full,2=half */ +int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */ +int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */ +int IrqModMaskOffset = 6; /* all ints moderated=default */ + +SK_BOOL IsConTypeDefined = SK_TRUE; +SK_BOOL IsLinkSpeedDefined = SK_TRUE; +SK_BOOL IsFlowCtrlDefined = SK_TRUE; +SK_BOOL IsRoleDefined = SK_TRUE; +SK_BOOL IsModeDefined = SK_TRUE; /* * The two parameters AutoNeg. and DuplexCap. map to one configuration * parameter. The mapping is described by this table: @@ -3155,6 +3951,15 @@ {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF }, {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} }; +SK_U32 IrqModMask[7][2] = + { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS }, + { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS }, + { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS }, + { IRQ_MASK_SP_RX , Y2_IRQ_MASK }, + { IRQ_MASK_TX_RX , Y2_DRIVER_IRQS }, + { IRQ_MASK_SP_TX , Y2_IRQ_MASK }, + { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK } }; + #define DC_BOTH 0 #define DC_FULL 1 #define DC_HALF 2 @@ -3194,7 +3999,7 @@ ** ** This ConType parameter is used for all ports of the adapter! */ - if ( (ConType != NULL) && + if ( (ConType != NULL) && (pAC->Index < SK_MAX_CARD_PARAM) && (ConType[pAC->Index] != NULL) ) { @@ -3220,40 +4025,40 @@ M_CurrPort.PMSMode = SK_MS_MODE_AUTO; M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO; } - } else if (strcmp(ConType[pAC->Index],"100FD")==0) { + } else if (strcmp(ConType[pAC->Index],"100FD")==0) { for (Port = 0; Port < SK_MAX_MACS; Port++) { M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL]; M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; M_CurrPort.PMSMode = SK_MS_MODE_AUTO; M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS; } - } else if (strcmp(ConType[pAC->Index],"100HD")==0) { + } else if (strcmp(ConType[pAC->Index],"100HD")==0) { for (Port = 0; Port < SK_MAX_MACS; Port++) { M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF]; M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; M_CurrPort.PMSMode = SK_MS_MODE_AUTO; M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS; } - } else if (strcmp(ConType[pAC->Index],"10FD")==0) { + } else if (strcmp(ConType[pAC->Index],"10FD")==0) { for (Port = 0; Port < SK_MAX_MACS; Port++) { M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL]; M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; M_CurrPort.PMSMode = SK_MS_MODE_AUTO; M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS; } - } else if (strcmp(ConType[pAC->Index],"10HD")==0) { + } else if (strcmp(ConType[pAC->Index],"10HD")==0) { for (Port = 0; Port < SK_MAX_MACS; Port++) { M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF]; M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; M_CurrPort.PMSMode = SK_MS_MODE_AUTO; M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS; } - } else { + } else { printk("sk98lin: Illegal value \"%s\" for ConType\n", ConType[pAC->Index]); IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */ } - } else { + } else { IsConTypeDefined = SK_FALSE; /* No ConType defined */ } @@ -3272,14 +4077,30 @@ } else if (strcmp(Speed_A[pAC->Index],"100")==0) { LinkSpeed = SK_LSPEED_100MBPS; } else if (strcmp(Speed_A[pAC->Index],"1000")==0) { - LinkSpeed = SK_LSPEED_1000MBPS; + if ((pAC->PciDev->vendor == 0x11ab ) && + (pAC->PciDev->device == 0x4350)) { + LinkSpeed = SK_LSPEED_100MBPS; + printk("sk98lin: Illegal value \"%s\" for Speed_A.\n" + "Gigabit speed not possible with this chip revision!", + Speed_A[pAC->Index]); + } else { + LinkSpeed = SK_LSPEED_1000MBPS; + } } else { printk("sk98lin: Illegal value \"%s\" for Speed_A\n", Speed_A[pAC->Index]); IsLinkSpeedDefined = SK_FALSE; } } else { - IsLinkSpeedDefined = SK_FALSE; + if ((pAC->PciDev->vendor == 0x11ab ) && + (pAC->PciDev->device == 0x4350)) { + /* Gigabit speed not supported + * Swith to speed 100 + */ + LinkSpeed = SK_LSPEED_100MBPS; + } else { + IsLinkSpeedDefined = SK_FALSE; + } } /* @@ -3374,9 +4195,6 @@ } if (!AutoSet && DupSet) { - printk("sk98lin: Port A: Duplex setting not" - " possible in\n default AutoNegotiation mode" - " (Sense).\n Using AutoNegotiation On\n"); AutoNeg = AN_ON; } @@ -3404,7 +4222,7 @@ FlowCtrl = SK_FLOW_MODE_NONE; } else { printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n", - FlowCtrl_A[pAC->Index]); + FlowCtrl_A[pAC->Index]); IsFlowCtrlDefined = SK_FALSE; } } else { @@ -3496,7 +4314,7 @@ ** Decide whether to set new config value if somethig valid has ** been received. */ - if (IsLinkSpeedDefined) { + if (IsLinkSpeedDefined) { pAC->GIni.GP[1].PLinkSpeed = LinkSpeed; } @@ -3572,9 +4390,6 @@ } if (!AutoSet && DupSet) { - printk("sk98lin: Port B: Duplex setting not" - " possible in\n default AutoNegotiation mode" - " (Sense).\n Using AutoNegotiation On\n"); AutoNeg = AN_ON; } @@ -3718,6 +4533,7 @@ /* ** Check the interrupt moderation parameters */ + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; if (Moderation[pAC->Index] != NULL) { if (strcmp(Moderation[pAC->Index], "") == 0) { pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; @@ -3731,70 +4547,49 @@ printk("sk98lin: Illegal value \"%s\" for Moderation.\n" " Disable interrupt moderation.\n", Moderation[pAC->Index]); - pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; - } - } else { - pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; - } - - if (Stats[pAC->Index] != NULL) { - if (strcmp(Stats[pAC->Index], "Yes") == 0) { - pAC->DynIrqModInfo.DisplayStats = SK_TRUE; - } else { - pAC->DynIrqModInfo.DisplayStats = SK_FALSE; } } else { - pAC->DynIrqModInfo.DisplayStats = SK_FALSE; +/* Set interrupt moderation if wished */ +#ifdef CONFIG_SK98LIN_STATINT + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC; +#endif } if (ModerationMask[pAC->Index] != NULL) { if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY; + IrqModMaskOffset = 0; } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_ONLY; + IrqModMaskOffset = 1; } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_ONLY; + IrqModMaskOffset = 2; } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX; + IrqModMaskOffset = 3; } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX; + IrqModMaskOffset = 3; } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX; + IrqModMaskOffset = 4; } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX; + IrqModMaskOffset = 4; } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX; + IrqModMaskOffset = 5; } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX; - } else if (strcmp(ModerationMask[pAC->Index], "RxTxSp") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP; - } else if (strcmp(ModerationMask[pAC->Index], "RxSpTx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP; - } else if (strcmp(ModerationMask[pAC->Index], "TxRxSp") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP; - } else if (strcmp(ModerationMask[pAC->Index], "TxSpRx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP; - } else if (strcmp(ModerationMask[pAC->Index], "SpTxRx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP; - } else if (strcmp(ModerationMask[pAC->Index], "SpRxTx") == 0) { - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP; - } else { /* some rubbish */ - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY; - } - } else { /* operator has stated nothing */ - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX; - } - - if (AutoSizing[pAC->Index] != NULL) { - if (strcmp(AutoSizing[pAC->Index], "On") == 0) { - pAC->DynIrqModInfo.AutoSizing = SK_FALSE; - } else { - pAC->DynIrqModInfo.AutoSizing = SK_FALSE; + IrqModMaskOffset = 5; + } else { /* some rubbish stated */ + // IrqModMaskOffset = 6; ->has been initialized + // already at the begin of this function... } - } else { /* operator has stated nothing */ - pAC->DynIrqModInfo.AutoSizing = SK_FALSE; + } + if (!CHIP_ID_YUKON_2(pAC)) { + pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0]; + } else { + pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1]; } + if (!CHIP_ID_YUKON_2(pAC)) { + pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT; + } else { + pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT; + } if (IntsPerSec[pAC->Index] != 0) { if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) || (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) { @@ -3803,28 +4598,25 @@ IntsPerSec[pAC->Index], C_INT_MOD_IPS_LOWER_RANGE, C_INT_MOD_IPS_UPPER_RANGE, - C_INTS_PER_SEC_DEFAULT); - pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT; + pAC->DynIrqModInfo.MaxModIntsPerSec); } else { pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index]; } - } else { - pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT; - } + } /* ** Evaluate upper and lower moderation threshold */ pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit = pAC->DynIrqModInfo.MaxModIntsPerSec + - (pAC->DynIrqModInfo.MaxModIntsPerSec / 2); + (pAC->DynIrqModInfo.MaxModIntsPerSec / 5); pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit = pAC->DynIrqModInfo.MaxModIntsPerSec - - (pAC->DynIrqModInfo.MaxModIntsPerSec / 2); - - pAC->DynIrqModInfo.PrevTimeVal = jiffies; /* initial value */ + (pAC->DynIrqModInfo.MaxModIntsPerSec / 5); + pAC->DynIrqModInfo.DynIrqModSampleInterval = + SK_DRV_MODERATION_TIMER_LENGTH; } /* GetConfiguration */ @@ -3860,45 +4652,6 @@ } } /* ProductStr */ -/***************************************************************************** - * - * StartDrvCleanupTimer - Start timer to check for descriptors which - * might be placed in descriptor ring, but - * havent been handled up to now - * - * Description: - * This function requests a HW-timer fo the Yukon card. The actions to - * perform when this timer expires, are located in the SkDrvEvent(). - * - * Returns: N/A - */ -static void -StartDrvCleanupTimer(SK_AC *pAC) { - SK_EVPARA EventParam; /* Event struct for timer event */ - - SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); - EventParam.Para32[0] = SK_DRV_RX_CLEANUP_TIMER; - SkTimerStart(pAC, pAC->IoBase, &pAC->DrvCleanupTimer, - SK_DRV_RX_CLEANUP_TIMER_LENGTH, - SKGE_DRV, SK_DRV_TIMER, EventParam); -} - -/***************************************************************************** - * - * StopDrvCleanupTimer - Stop timer to check for descriptors - * - * Description: - * This function requests a HW-timer fo the Yukon card. The actions to - * perform when this timer expires, are located in the SkDrvEvent(). - * - * Returns: N/A - */ -static void -StopDrvCleanupTimer(SK_AC *pAC) { - SkTimerStop(pAC, pAC->IoBase, &pAC->DrvCleanupTimer); - SK_MEMSET((char *) &pAC->DrvCleanupTimer, 0, sizeof(SK_TIMER)); -} - /****************************************************************************/ /* functions for common modules *********************************************/ /****************************************************************************/ @@ -3987,7 +4740,9 @@ SK_U64 SkOsGetTime(SK_AC *pAC) { SK_U64 PrivateJiffies; + SkOsGetTimeCurrent(pAC, &PrivateJiffies); + return PrivateJiffies; } /* SkOsGetTime */ @@ -4142,28 +4897,31 @@ * */ int SkDrvEvent( -SK_AC *pAC, /* pointer to adapter context */ -SK_IOC IoC, /* io-context */ -SK_U32 Event, /* event-id */ -SK_EVPARA Param) /* event-parameter */ -{ -SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */ -struct sk_buff *pMsg; /* pointer to a message block */ -int FromPort; /* the port from which we switch away */ -int ToPort; /* the port we switch to */ -SK_EVPARA NewPara; /* parameter for further events */ -int Stat; -unsigned long Flags; -SK_BOOL DualNet; +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* IO control context */ +SK_U32 Event, /* event-id */ +SK_EVPARA Param) /* event-parameter */ +{ + SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */ + struct sk_buff *pMsg; /* pointer to a message block */ + SK_EVPARA NewPara; /* parameter for further events */ + SK_BOOL DualNet; + SK_U32 Reason; + unsigned long Flags; + int FromPort; /* the port from which we switch away */ + int ToPort; /* the port we switch to */ + int Stat; +#ifdef CONFIG_SK98LIN_NAPI + int WorkToDo = 1; /* min(*budget, dev->quota); */ + int WorkDone = 0; +#endif switch (Event) { case SK_DRV_ADAP_FAIL: SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("ADAPTER FAIL EVENT\n")); printk("%s: Adapter failed.\n", pAC->dev[0]->name); - /* disable interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, 0); - /* cgoos */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */ break; case SK_DRV_PORT_FAIL: FromPort = Param.Para32[0]; @@ -4174,10 +4932,8 @@ } else { printk("%s: Port B failed.\n", pAC->dev[1]->name); } - /* cgoos */ break; - case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */ - /* action list 4 */ + case SK_DRV_PORT_RESET: FromPort = Param.Para32[0]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("PORT RESET EVENT, Port: %d ", FromPort)); @@ -4186,176 +4942,187 @@ spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - - SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); + } else { + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); + } pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING; spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - /* clear rx ring from received frames */ - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); - - ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); +#endif + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + } spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - /* tschilling: Handling of return value inserted. */ - if (SkGeInitPort(pAC, IoC, FromPort)) { - if (FromPort == 0) { - printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); - } else { - printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStart(pAC, IoC, FromPort); + } else { + /* tschilling: Handling of return value inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort)) { + if (FromPort == 0) { + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); + } } + SkAddrMcUpdate(pAC,IoC, FromPort); + PortReInitBmu(pAC, FromPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + CLEAR_AND_START_RX(FromPort); } - SkAddrMcUpdate(pAC,IoC, FromPort); - PortReInitBmu(pAC, FromPort); - SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); - ClearAndStartRx(pAC, FromPort); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); break; - case SK_DRV_NET_UP: /* SK_U32 PortIdx */ - /* action list 5 */ + case SK_DRV_NET_UP: FromPort = Param.Para32[0]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("NET UP EVENT, Port: %d ", Param.Para32[0])); - /* Mac update */ - SkAddrMcUpdate(pAC,IoC, FromPort); - + ("NET UP EVENT, Port: %d ", FromPort)); + SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */ if (DoPrintInterfaceChange) { - printk("%s: network connection up using" - " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]); + printk("%s: network connection up using port %c\n", + pAC->dev[FromPort]->name, 'A'+FromPort); - /* tschilling: Values changed according to LinkSpeedUsed. */ - Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed; - if (Stat == SK_LSPEED_STAT_10MBPS) { - printk(" speed: 10\n"); - } else if (Stat == SK_LSPEED_STAT_100MBPS) { - printk(" speed: 100\n"); - } else if (Stat == SK_LSPEED_STAT_1000MBPS) { - printk(" speed: 1000\n"); - } else { - printk(" speed: unknown\n"); - } + /* tschilling: Values changed according to LinkSpeedUsed. */ + Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed; + if (Stat == SK_LSPEED_STAT_10MBPS) { + printk(" speed: 10\n"); + } else if (Stat == SK_LSPEED_STAT_100MBPS) { + printk(" speed: 100\n"); + } else if (Stat == SK_LSPEED_STAT_1000MBPS) { + printk(" speed: 1000\n"); + } else { + printk(" speed: unknown\n"); + } + Stat = pAC->GIni.GP[FromPort].PLinkModeStatus; + if ((Stat == SK_LMODE_STAT_AUTOHALF) || + (Stat == SK_LMODE_STAT_AUTOFULL)) { + printk(" autonegotiation: yes\n"); + } else { + printk(" autonegotiation: no\n"); + } - Stat = pAC->GIni.GP[FromPort].PLinkModeStatus; - if (Stat == SK_LMODE_STAT_AUTOHALF || - Stat == SK_LMODE_STAT_AUTOFULL) { - printk(" autonegotiation: yes\n"); - } - else { - printk(" autonegotiation: no\n"); - } - if (Stat == SK_LMODE_STAT_AUTOHALF || - Stat == SK_LMODE_STAT_HALF) { - printk(" duplex mode: half\n"); - } - else { - printk(" duplex mode: full\n"); - } - Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus; - if (Stat == SK_FLOW_STAT_REM_SEND ) { - printk(" flowctrl: remote send\n"); - } - else if (Stat == SK_FLOW_STAT_LOC_SEND ){ - printk(" flowctrl: local send\n"); - } - else if (Stat == SK_FLOW_STAT_SYMMETRIC ){ - printk(" flowctrl: symmetric\n"); - } - else { - printk(" flowctrl: none\n"); - } - - /* tschilling: Check against CopperType now. */ - if ((pAC->GIni.GICopperType == SK_TRUE) && - (pAC->GIni.GP[FromPort].PLinkSpeedUsed == - SK_LSPEED_STAT_1000MBPS)) { - Stat = pAC->GIni.GP[FromPort].PMSStatus; - if (Stat == SK_MS_STAT_MASTER ) { - printk(" role: master\n"); + if ((Stat == SK_LMODE_STAT_AUTOHALF) || + (Stat == SK_LMODE_STAT_HALF)) { + printk(" duplex mode: half\n"); + } else { + printk(" duplex mode: full\n"); } - else if (Stat == SK_MS_STAT_SLAVE ) { - printk(" role: slave\n"); + + Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus; + if (Stat == SK_FLOW_STAT_REM_SEND ) { + printk(" flowctrl: remote send\n"); + } else if (Stat == SK_FLOW_STAT_LOC_SEND ) { + printk(" flowctrl: local send\n"); + } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) { + printk(" flowctrl: symmetric\n"); + } else { + printk(" flowctrl: none\n"); } - else { - printk(" role: ???\n"); + + /* tschilling: Check against CopperType now. */ + if ((pAC->GIni.GICopperType == SK_TRUE) && + (pAC->GIni.GP[FromPort].PLinkSpeedUsed == + SK_LSPEED_STAT_1000MBPS)) { + Stat = pAC->GIni.GP[FromPort].PMSStatus; + if (Stat == SK_MS_STAT_MASTER ) { + printk(" role: master\n"); + } else if (Stat == SK_MS_STAT_SLAVE ) { + printk(" role: slave\n"); + } else { + printk(" role: ???\n"); + } } - } - /* - Display dim (dynamic interrupt moderation) - informations - */ - if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) - printk(" irq moderation: static (%d ints/sec)\n", + /* Display interrupt moderation informations */ + if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) { + printk(" irq moderation: static (%d ints/sec)\n", pAC->DynIrqModInfo.MaxModIntsPerSec); - else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) - printk(" irq moderation: dynamic (%d ints/sec)\n", + } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + printk(" irq moderation: dynamic (%d ints/sec)\n", pAC->DynIrqModInfo.MaxModIntsPerSec); - else - printk(" irq moderation: disabled\n"); + } else { + printk(" irq moderation: disabled\n"); + } + +#ifdef NETIF_F_TSO + if (CHIP_ID_YUKON_2(pAC)) { + if (pAC->dev[FromPort]->features & NETIF_F_TSO) { + printk(" tcp offload: enabled\n"); + } else { + printk(" tcp offload: disabled\n"); + } + } +#endif + if (pAC->dev[FromPort]->features & NETIF_F_SG) { + printk(" scatter-gather: enabled\n"); + } else { + printk(" scatter-gather: disabled\n"); + } -#ifdef SK_ZEROCOPY - if (pAC->ChipsetType) -#ifdef USE_SK_TX_CHECKSUM - printk(" scatter-gather: enabled\n"); -#else - printk(" tx-checksum: disabled\n"); -#endif - else - printk(" scatter-gather: disabled\n"); -#else - printk(" scatter-gather: disabled\n"); -#endif + if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) { + printk(" tx-checksum: enabled\n"); + } else { + printk(" tx-checksum: disabled\n"); + } -#ifndef USE_SK_RX_CHECKSUM - printk(" rx-checksum: disabled\n"); + if (pAC->RxPort[FromPort].UseRxCsum) { + printk(" rx-checksum: enabled\n"); + } else { + printk(" rx-checksum: disabled\n"); + } +#ifdef CONFIG_SK98LIN_NAPI + printk(" rx-polling: enabled\n"); #endif - } else { - DoPrintInterfaceChange = SK_TRUE; - } + DoPrintInterfaceChange = SK_TRUE; + } - if ((Param.Para32[0] != pAC->ActivePort) && - (pAC->RlmtNets == 1)) { + if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) { NewPara.Para32[0] = pAC->ActivePort; - NewPara.Para32[1] = Param.Para32[0]; - SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN, - NewPara); + NewPara.Para32[1] = FromPort; + SkEventQueue(pAC,SKGE_DRV,SK_DRV_SWITCH_INTERN,NewPara); } /* Inform the world that link protocol is up. */ - pAC->dev[Param.Para32[0]]->flags |= IFF_RUNNING; - + netif_wake_queue(pAC->dev[0]); + pAC->dev[FromPort]->flags |= IFF_RUNNING; break; - case SK_DRV_NET_DOWN: /* SK_U32 Reason */ - /* action list 7 */ + case SK_DRV_NET_DOWN: + Reason = Param.Para32[0]; + FromPort = Param.Para32[1]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("NET DOWN EVENT ")); if (DoPrintInterfaceChange) { - printk("%s: network connection down\n", - pAC->dev[Param.Para32[1]]->name); + if (pAC->dev[FromPort]->flags & IFF_RUNNING) { + printk("%s: network connection down\n", + pAC->dev[FromPort]->name); + } } else { DoPrintInterfaceChange = SK_TRUE; } - pAC->dev[Param.Para32[1]]->flags &= ~IFF_RUNNING; + pAC->dev[FromPort]->flags &= ~IFF_RUNNING; break; - case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("PORT SWITCH HARD ")); - case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ - /* action list 6 */ - printk("%s: switching to port %c\n", pAC->dev[0]->name, - 'A'+Param.Para32[1]); - case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + case SK_DRV_SWITCH_HARD: /* FALL THRU */ + case SK_DRV_SWITCH_SOFT: /* FALL THRU */ + case SK_DRV_SWITCH_INTERN: FromPort = Param.Para32[0]; - ToPort = Param.Para32[1]; + ToPort = Param.Para32[1]; + printk("%s: switching from port %c to port %c\n", + pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort); SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ", FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort)); @@ -4367,18 +5134,33 @@ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); - SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); - SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); + SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_HARD_RST); + } + else { + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); + } spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */ - ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */ - ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); - ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]); + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo); + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */ + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */ +#endif + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]); + } + spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); @@ -4405,61 +5187,59 @@ break; } #endif - /* tschilling: Handling of return values inserted. */ - if (SkGeInitPort(pAC, IoC, FromPort) || - SkGeInitPort(pAC, IoC, ToPort)) { - printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name); + if (!CHIP_ID_YUKON_2(pAC)) { + /* tschilling: Handling of return values inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort) || + SkGeInitPort(pAC, IoC, ToPort)) { + printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name); + } } if (Event == SK_DRV_SWITCH_SOFT) { SkMacRxTxEnable(pAC, IoC, FromPort); } + SkMacRxTxEnable(pAC, IoC, ToPort); SkAddrSwap(pAC, IoC, FromPort, ToPort); SkAddrMcUpdate(pAC, IoC, FromPort); SkAddrMcUpdate(pAC, IoC, ToPort); - PortReInitBmu(pAC, FromPort); - PortReInitBmu(pAC, ToPort); - SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); - SkGePollTxD(pAC, IoC, ToPort, SK_TRUE); - ClearAndStartRx(pAC, FromPort); - ClearAndStartRx(pAC, ToPort); + + if (!CHIP_ID_YUKON_2(pAC)) { + PortReInitBmu(pAC, FromPort); + PortReInitBmu(pAC, ToPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + SkGePollTxD(pAC, IoC, ToPort, SK_TRUE); + CLEAR_AND_START_RX(FromPort); + CLEAR_AND_START_RX(ToPort); + } else { + SkY2PortStart(pAC, IoC, FromPort); + SkY2PortStart(pAC, IoC, ToPort); + } spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); break; case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */ - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("RLS ")); + SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS ")); pRlmtMbuf = (SK_MBUF*) Param.pParaPtr; pMsg = (struct sk_buff*) pRlmtMbuf->pOs; skb_put(pMsg, pRlmtMbuf->Length); - if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW], - pMsg) < 0) - - DEV_KFREE_SKB_ANY(pMsg); + if (!CHIP_ID_YUKON_2(pAC)) { + if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW], + pMsg) < 0) { + DEV_KFREE_SKB_ANY(pMsg); + } + } else { + if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) { + DEV_KFREE_SKB_ANY(pMsg); + } + } break; case SK_DRV_TIMER: if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) { - /* - ** expiration of the moderation timer implies that - ** dynamic moderation is to be applied - */ + /* check what IRQs are to be moderated */ SkDimStartModerationTimer(pAC); SkDimModerate(pAC); - if (pAC->DynIrqModInfo.DisplayStats) { - SkDimDisplayModerationSettings(pAC); - } - } else if (Param.Para32[0] == SK_DRV_RX_CLEANUP_TIMER) { - /* - ** check if we need to check for descriptors which - ** haven't been handled the last millisecs - */ - StartDrvCleanupTimer(pAC); - if (pAC->GIni.GIMacsFound == 2) { - ReceiveIrq(pAC, &pAC->RxPort[1], SK_FALSE); - } - ReceiveIrq(pAC, &pAC->RxPort[0], SK_FALSE); } else { printk("Expiration of unknown timer\n"); } @@ -4523,8 +5303,6 @@ } /* SkErrorLog */ -#ifdef SK_DIAG_SUPPORT - /***************************************************************************** * * SkDrvEnterDiagMode - handles DIAG attach request @@ -4592,16 +5370,16 @@ sizeof(SK_PNMI_STRUCT_DATA)); pAc->DiagModeActive = DIAG_NOTACTIVE; pAc->Pnmi.DiagAttached = SK_DIAG_IDLE; - if (pAc->WasIfUp[0] == SK_TRUE) { - pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ + if (pAc->WasIfUp[0] == SK_TRUE) { + pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ DoPrintInterfaceChange = SK_FALSE; - SkDrvInitAdapter(pAc, 0); /* first device */ - } - if (pAc->WasIfUp[1] == SK_TRUE) { - pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ + SkDrvInitAdapter(pAc, 0); /* first device */ + } + if (pAc->WasIfUp[1] == SK_TRUE) { + pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ DoPrintInterfaceChange = SK_FALSE; - SkDrvInitAdapter(pAc, 1); /* second device */ - } + SkDrvInitAdapter(pAc, 1); /* second device */ + } return(0); } @@ -4746,14 +5524,25 @@ } /* SkDrvInitAdapter */ -#endif +static int __init sk98lin_init(void) +{ + return pci_module_init(&sk98lin_driver); +} + +static void __exit sk98lin_cleanup(void) +{ + pci_unregister_driver(&sk98lin_driver); +} + +module_init(sk98lin_init); +module_exit(sk98lin_cleanup); + #ifdef DEBUG /****************************************************************************/ /* "debug only" section *****************************************************/ /****************************************************************************/ - /***************************************************************************** * * DumpMsg - print a frame @@ -4764,9 +5553,11 @@ * Returns: N/A * */ -static void DumpMsg(struct sk_buff *skb, char *str) +static void DumpMsg( +struct sk_buff *skb, /* linux' socket buffer */ +char *str) /* additional msg string */ { - int msglen; + int msglen = (skb->len > 64) ? 64 : skb->len; if (skb == NULL) { printk("DumpMsg(): NULL-Message\n"); @@ -4778,19 +5569,14 @@ return; } - msglen = skb->len; - if (msglen > 64) - msglen = 64; - - printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len); - + printk("DumpMsg: PhysPage: %p\n", + page_address(virt_to_page(skb->data))); + printk("--- Begin of message from %s , len %d (from %d) ----\n", + str, msglen, skb->len); DumpData((char *)skb->data, msglen); - printk("------- End of message ---------\n"); } /* DumpMsg */ - - /***************************************************************************** * * DumpData - print a data area @@ -4802,23 +5588,22 @@ * Returns: N/A * */ -static void DumpData(char *p, int size) -{ -register int i; -int haddr, addr; -char hex_buffer[180]; -char asc_buffer[180]; -char HEXCHAR[] = "0123456789ABCDEF"; - - addr = 0; - haddr = 0; - hex_buffer[0] = 0; - asc_buffer[0] = 0; +static void DumpData( +char *p, /* pointer to area containing the data */ +int size) /* the size of that data area in bytes */ +{ + register int i; + int haddr = 0, addr = 0; + char hex_buffer[180] = { '\0' }; + char asc_buffer[180] = { '\0' }; + char HEXCHAR[] = "0123456789ABCDEF"; + for (i=0; i < size; ) { - if (*p >= '0' && *p <='z') + if (*p >= '0' && *p <='z') { asc_buffer[addr] = *p; - else + } else { asc_buffer[addr] = '.'; + } addr++; asc_buffer[addr] = 0; hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4]; @@ -4844,27 +5629,24 @@ * DumpLong - print a data area as long values * * Description: - * This function prints a area of data to the system logfile/to the + * This function prints a long variable to the system logfile/to the * console. * * Returns: N/A * */ -static void DumpLong(char *pc, int size) -{ -register int i; -int haddr, addr; -char hex_buffer[180]; -char asc_buffer[180]; -char HEXCHAR[] = "0123456789ABCDEF"; -long *p; -int l; - - addr = 0; - haddr = 0; - hex_buffer[0] = 0; - asc_buffer[0] = 0; - p = (long*) pc; +static void DumpLong( +char *pc, /* location of the variable to print */ +int size) /* how large is the variable? */ +{ + register int i; + int haddr = 0, addr = 0; + char hex_buffer[180] = { '\0' }; + char asc_buffer[180] = { '\0' }; + char HEXCHAR[] = "0123456789ABCDEF"; + long *p = (long*) pc; + int l; + for (i=0; i < size; ) { l = (long) *p; hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf]; @@ -4898,319 +5680,8 @@ #endif -static int __devinit skge_probe_one(struct pci_dev *pdev, - const struct pci_device_id *ent) -{ - SK_AC *pAC; - DEV_NET *pNet = NULL; - struct net_device *dev = NULL; -#ifdef CONFIG_PROC_FS - struct proc_dir_entry *pProcFile; -#endif - static int boards_found = 0; - int error = -ENODEV; - - if (pci_enable_device(pdev)) - goto out; - - /* Configure DMA attributes. */ - if (pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL) && - pci_set_dma_mask(pdev, (u64) 0xffffffff)) - goto out_disable_device; - - - if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) { - printk(KERN_ERR "Unable to allocate etherdev " - "structure!\n"); - goto out_disable_device; - } - - pNet = dev->priv; - pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); - if (!pNet->pAC) { - printk(KERN_ERR "Unable to allocate adapter " - "structure!\n"); - goto out_free_netdev; - } - - memset(pNet->pAC, 0, sizeof(SK_AC)); - pAC = pNet->pAC; - pAC->PciDev = pdev; - pAC->PciDevId = pdev->device; - pAC->dev[0] = dev; - pAC->dev[1] = dev; - sprintf(pAC->Name, "SysKonnect SK-98xx"); - pAC->CheckQueue = SK_FALSE; - - pNet->Mtu = 1500; - pNet->Up = 0; - dev->irq = pdev->irq; - error = SkGeInitPCI(pAC); - if (error) { - printk("SKGE: PCI setup failed: %i\n", error); - goto out_free_netdev; - } - - SET_MODULE_OWNER(dev); - dev->open = &SkGeOpen; - dev->stop = &SkGeClose; - dev->hard_start_xmit = &SkGeXmit; - dev->get_stats = &SkGeStats; - dev->last_stats = &SkGeStats; - dev->set_multicast_list = &SkGeSetRxMode; - dev->set_mac_address = &SkGeSetMacAddr; - dev->do_ioctl = &SkGeIoctl; - dev->change_mtu = &SkGeChangeMtu; - dev->flags &= ~IFF_RUNNING; - SET_NETDEV_DEV(dev, &pdev->dev); - -#ifdef SK_ZEROCOPY -#ifdef USE_SK_TX_CHECKSUM - if (pAC->ChipsetType) { - /* Use only if yukon hardware */ - /* SK and ZEROCOPY - fly baby... */ - dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; - } -#endif -#endif - - pAC->Index = boards_found++; - - if (SkGeBoardInit(dev, pAC)) - goto out_free_netdev; - - /* Register net device */ - if (register_netdev(dev)) { - printk(KERN_ERR "SKGE: Could not register device.\n"); - goto out_free_resources; - } - - /* Print adapter specific string from vpd */ - ProductStr(pAC); - printk("%s: %s\n", dev->name, pAC->DeviceStr); - - /* Print configuration settings */ - printk(" PrefPort:%c RlmtMode:%s\n", - 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, - (pAC->RlmtMode==0) ? "Check Link State" : - ((pAC->RlmtMode==1) ? "Check Link State" : - ((pAC->RlmtMode==3) ? "Check Local Port" : - ((pAC->RlmtMode==7) ? "Check Segmentation" : - ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); - - SkGeYellowLED(pAC, pAC->IoBase, 1); - - - memcpy(&dev->dev_addr, &pAC->Addr.Net[0].CurrentMacAddress, 6); - -#ifdef CONFIG_PROC_FS - pProcFile = create_proc_entry(dev->name, S_IRUGO, pSkRootDir); - if (pProcFile) { - pProcFile->proc_fops = &sk_proc_fops; - pProcFile->data = dev; - pProcFile->owner = THIS_MODULE; - } -#endif - - pNet->PortNr = 0; - pNet->NetNr = 0; - - boards_found++; - - /* More then one port found */ - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { - if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) { - printk(KERN_ERR "Unable to allocate etherdev " - "structure!\n"); - goto out; - } - - pAC->dev[1] = dev; - pNet = dev->priv; - pNet->PortNr = 1; - pNet->NetNr = 1; - pNet->pAC = pAC; - pNet->Mtu = 1500; - pNet->Up = 0; - - dev->open = &SkGeOpen; - dev->stop = &SkGeClose; - dev->hard_start_xmit = &SkGeXmit; - dev->get_stats = &SkGeStats; - dev->last_stats = &SkGeStats; - dev->set_multicast_list = &SkGeSetRxMode; - dev->set_mac_address = &SkGeSetMacAddr; - dev->do_ioctl = &SkGeIoctl; - dev->change_mtu = &SkGeChangeMtu; - dev->flags &= ~IFF_RUNNING; - -#ifdef SK_ZEROCOPY -#ifdef USE_SK_TX_CHECKSUM - if (pAC->ChipsetType) { - /* SG and ZEROCOPY - fly baby... */ - dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; - } -#endif -#endif - - if (register_netdev(dev)) { - printk(KERN_ERR "SKGE: Could not register device.\n"); - free_netdev(dev); - pAC->dev[1] = pAC->dev[0]; - } else { -#ifdef CONFIG_PROC_FS - pProcFile = create_proc_entry(dev->name, S_IRUGO, - pSkRootDir); - if (pProcFile) { - pProcFile->proc_fops = &sk_proc_fops; - pProcFile->data = dev; - pProcFile->owner = THIS_MODULE; - } -#endif - - memcpy(&dev->dev_addr, - &pAC->Addr.Net[1].CurrentMacAddress, 6); - - printk("%s: %s\n", dev->name, pAC->DeviceStr); - printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); - } - } - - /* Save the hardware revision */ - pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + - (pAC->GIni.GIPciHwRev & 0x0F); - - /* Set driver globals */ - pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME; - pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE; - - memset(&pAC->PnmiBackup, 0, sizeof(SK_PNMI_STRUCT_DATA)); - memcpy(&pAC->PnmiBackup, &pAC->PnmiStruct, sizeof(SK_PNMI_STRUCT_DATA)); - - pci_set_drvdata(pdev, dev); - return 0; - - out_free_resources: - FreeResources(dev); - out_free_netdev: - free_netdev(dev); - out_disable_device: - pci_disable_device(pdev); - out: - return error; -} - -static void __devexit skge_remove_one(struct pci_dev *pdev) -{ - struct net_device *dev = pci_get_drvdata(pdev); - DEV_NET *pNet = (DEV_NET *) dev->priv; - SK_AC *pAC = pNet->pAC; - int have_second_mac = 0; - - if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2) - have_second_mac = 1; - - remove_proc_entry(dev->name, pSkRootDir); - unregister_netdev(dev); - if (have_second_mac) { - remove_proc_entry(pAC->dev[1]->name, pSkRootDir); - unregister_netdev(pAC->dev[1]); - } - - SkGeYellowLED(pAC, pAC->IoBase, 0); - - if (pAC->BoardLevel == SK_INIT_RUN) { - SK_EVPARA EvPara; - unsigned long Flags; - - /* board is still alive */ - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - EvPara.Para32[0] = 0; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - EvPara.Para32[0] = 1; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); - /* disable interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, 0); - SkGeDeInit(pAC, pAC->IoBase); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - pAC->BoardLevel = SK_INIT_DATA; - /* We do NOT check here, if IRQ was pending, of course*/ - } - - if (pAC->BoardLevel == SK_INIT_IO) { - /* board is still alive */ - SkGeDeInit(pAC, pAC->IoBase); - pAC->BoardLevel = SK_INIT_DATA; - } - - FreeResources(dev); - free_netdev(dev); - if (have_second_mac) - free_netdev(pAC->dev[1]); - kfree(pAC); -} - -static struct pci_device_id skge_pci_tbl[] = { - { PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_SYSKONNECT, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_SYSKONNECT, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_DLINK, 0x4c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_MARVELL, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, -#if 0 /* don't handle Yukon2 cards at the moment -- mlindner@syskonnect.de */ - { PCI_VENDOR_ID_MARVELL, 0x4360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_MARVELL, 0x4361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, -#endif - { PCI_VENDOR_ID_MARVELL, 0x5005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_CNET, 0x434e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { PCI_VENDOR_ID_LINKSYS, 0x1064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, - { 0, } -}; - -static struct pci_driver skge_driver = { - .name = "skge", - .id_table = skge_pci_tbl, - .probe = skge_probe_one, - .remove = __devexit_p(skge_remove_one), -}; - -static int __init skge_init(void) -{ - int error; - -#ifdef CONFIG_PROC_FS - memcpy(&SK_Root_Dir_entry, BOOT_STRING, sizeof(SK_Root_Dir_entry) - 1); - - pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net); - if (!pSkRootDir) { - printk(KERN_WARNING "Unable to create /proc/net/%s", - SK_Root_Dir_entry); - return -ENOMEM; - } - pSkRootDir->owner = THIS_MODULE; -#endif - - error = pci_module_init(&skge_driver); - if (error) { -#ifdef CONFIG_PROC_FS - remove_proc_entry(pSkRootDir->name, proc_net); -#endif - } - - return error; -} - -static void __exit skge_exit(void) -{ - pci_unregister_driver(&skge_driver); -#ifdef CONFIG_PROC_FS - remove_proc_entry(pSkRootDir->name, proc_net); -#endif -} - -module_init(skge_init); -module_exit(skge_exit); +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/skgehwt.c linux-new/drivers/net/sk98lin/skgehwt.c --- linux/drivers/net/sk98lin/skgehwt.c 2004-08-14 12:56:14.000000000 +0200 +++ linux-new/drivers/net/sk98lin/skgehwt.c 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skgehwt.c * Project: Gigabit Ethernet Adapters, Event Scheduler Module - * Version: $Revision: 1.15 $ - * Date: $Date: 2003/09/16 13:41:23 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2004/05/28 13:39:04 $ * Purpose: Hardware Timer * ******************************************************************************/ @@ -11,7 +11,7 @@ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect GmbH. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,7 +27,7 @@ */ #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "@(#) $Id: skgehwt.c,v 1.15 2003/09/16 13:41:23 rschmidt Exp $ (C) Marvell."; + "@(#) $Id: skgehwt.c,v 2.2 2004/05/28 13:39:04 rschmidt Exp $ (C) Marvell."; #endif #include "h/skdrv1st.h" /* Driver Specific Definitions */ @@ -44,10 +44,10 @@ /* * Prototypes of local functions. */ -#define SK_HWT_MAX (65000) +#define SK_HWT_MAX 65000UL * 160 /* ca. 10 sec. */ /* correction factor */ -#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100) +#define SK_HWT_FAC (10 * (SK_U32)pAC->GIni.GIHstClkFact / 16) /* * Initialize hardware timer. @@ -73,29 +73,21 @@ void SkHwtStart( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc, /* IoContext */ -SK_U32 Time) /* Time in units of 16us to load the timer with. */ +SK_U32 Time) /* Time in usec to load the timer */ { - SK_U32 Cnt; - if (Time > SK_HWT_MAX) Time = SK_HWT_MAX; pAC->Hwt.TStart = Time; pAC->Hwt.TStop = 0L; - Cnt = Time; - - /* - * if time < 16 us - * time = 16 us - */ - if (!Cnt) { - Cnt++; + if (!Time) { + Time = 1L; } - SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC); - - SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer. */ + SK_OUT32(Ioc, B2_TI_INI, Time * SK_HWT_FAC); + + SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer */ pAC->Hwt.TActive = SK_TRUE; } @@ -109,13 +101,12 @@ SK_IOC Ioc) /* IoContext */ { SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP); - + SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ); pAC->Hwt.TActive = SK_FALSE; } - /* * Stop hardware timer and read time elapsed since last start. * @@ -129,6 +120,9 @@ { SK_U32 TRead; SK_U32 IStatus; + SK_U32 TimerInt; + + TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT; if (pAC->Hwt.TActive) { @@ -139,15 +133,15 @@ SK_IN32(Ioc, B0_ISRC, &IStatus); - /* Check if timer expired (or wraped around) */ - if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) { - + /* Check if timer expired (or wrapped around) */ + if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) { + SkHwtStop(pAC, Ioc); - + pAC->Hwt.TStop = pAC->Hwt.TStart; } else { - + pAC->Hwt.TStop = pAC->Hwt.TStart - TRead; } } @@ -162,9 +156,9 @@ SK_IOC Ioc) /* IoContext */ { SkHwtStop(pAC, Ioc); - + pAC->Hwt.TStop = pAC->Hwt.TStart; - + SkTimerDone(pAC, Ioc); } diff -ruN linux/drivers/net/sk98lin/skgeinit.c linux-new/drivers/net/sk98lin/skgeinit.c --- linux/drivers/net/sk98lin/skgeinit.c 2004-08-14 12:55:33.000000000 +0200 +++ linux-new/drivers/net/sk98lin/skgeinit.c 2004-08-26 10:27:59.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skgeinit.c * Project: Gigabit Ethernet Adapters, Common Modules - * Version: $Revision: 1.97 $ - * Date: $Date: 2003/10/02 16:45:31 $ + * Version: $Revision: 2.56 $ + * Date: $Date: 2004/08/13 09:38:27 $ * Purpose: Contains functions to initialize the adapter * ******************************************************************************/ @@ -11,13 +11,12 @@ /****************************************************************************** * * (C)Copyright 1998-2002 SysKonnect. - * (C)Copyright 2002-2003 Marvell. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ @@ -31,7 +30,7 @@ #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "@(#) $Id: skgeinit.c,v 1.97 2003/10/02 16:45:31 rschmidt Exp $ (C) Marvell."; + "@(#) $Id: skgeinit.c,v 2.56 2004/08/13 09:38:27 rschmidt Exp $ (C) Marvell."; #endif struct s_QOffTab { @@ -59,6 +58,101 @@ /****************************************************************************** * + * SkGePortVlan() - Enable / Disable VLAN support + * + * Description: + * Enable or disable the VLAN support of the selected port. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * Currently this function is only supported on Yukon-2/EC adapters. + * + * Returns: + * nothing + */ +void SkGePortVlan( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port number */ +SK_BOOL Enable) /* Flag */ +{ + if (CHIP_ID_YUKON_2(pAC)) { + if (Enable) { + SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); + } + else { + SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); + } + } +} + + +/****************************************************************************** + * + * SkGeRxRss() - Enable / Disable RSS Hash Calculation + * + * Description: + * Enable or disable the RSS hash calculation of the selected port. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * Currently this function is only supported on Yukon-2/EC adapters. + * + * Returns: + * nothing + */ +void SkGeRxRss( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port number */ +SK_BOOL Enable) /* Flag */ +{ + if (CHIP_ID_YUKON_2(pAC)) { + if (Enable) { + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR), + BMU_ENA_RX_RSS_HASH); + } + else { + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR), + BMU_DIS_RX_RSS_HASH); + } + } +} + +/****************************************************************************** + * + * SkGeRxCsum() - Enable / Disable Receive Checksum + * + * Description: + * Enable or disable the checksum of the selected port. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * Currently this function is only supported on Yukon-2/EC adapters. + * + * Returns: + * nothing + */ +void SkGeRxCsum( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port number */ +SK_BOOL Enable) /* Flag */ +{ + if (CHIP_ID_YUKON_2(pAC)) { + if (Enable) { + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR), + BMU_ENA_RX_CHKSUM); + } + else { + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR), + BMU_DIS_RX_CHKSUM); + } + } +} + + +/****************************************************************************** + * * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring * * Description: @@ -71,8 +165,8 @@ * nothing */ void SkGePollRxD( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ { @@ -80,8 +174,8 @@ pPrt = &pAC->GIni.GP[Port]; - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ? - CSR_ENA_POL : CSR_DIS_POL); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ? + CSR_ENA_POL : CSR_DIS_POL)); } /* SkGePollRxD */ @@ -99,8 +193,8 @@ * nothing */ void SkGePollTxD( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ { @@ -114,7 +208,7 @@ if (pPrt->PXSQSize != 0) { SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord); } - + if (pPrt->PXAQSize != 0) { SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord); } @@ -135,8 +229,8 @@ * nothing */ void SkGeYellowLED( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int State) /* yellow LED state, 0 = OFF, 0 != ON */ { if (State == 0) { @@ -169,8 +263,8 @@ * nothing */ void SkGeXmitLED( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Led, /* offset to the LED Init Value register */ int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ { @@ -197,7 +291,7 @@ SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF); break; } - + /* * 1000BT: The Transmit LED is driven by the PHY. * But the default LED configuration is used for @@ -227,7 +321,7 @@ * 1: configuration error */ static int DoCalcAddr( -SK_AC *pAC, /* adapter context */ +SK_AC *pAC, /* Adapter Context */ SK_GEPORT SK_FAR *pPrt, /* port index */ int QuSize, /* size of the queue to configure in kB */ SK_U32 SK_FAR *StartVal, /* start value for address calculation */ @@ -264,12 +358,40 @@ /****************************************************************************** * + * SkGeRoundQueueSize() - Round the given queue size to the adpaters QZ units + * + * Description: + * This function rounds the given queue size in kBs to adapter specific + * queue size units (Genesis and Yukon: 8kB, Yukon-2/EC 1kB). + * + * Returns: + * the rounded queue size in kB + */ +static int SkGeRoundQueueSize( +SK_AC *pAC, /* Adapter Context */ +int QueueSizeKB) /* Queue size in kB */ +{ + int QueueSizeSteps; + + if (CHIP_ID_YUKON_2(pAC)) { + QueueSizeSteps = QZ_STEP_Y2; + } + else { + QueueSizeSteps = QZ_STEP; + } + + return ((QueueSizeKB + QueueSizeSteps-1) & ~(QueueSizeSteps-1)); +} /* SkGeRoundQueueSize */ + + +/****************************************************************************** + * * SkGeInitAssignRamToQueues() - allocate default queue sizes * * Description: * This function assigns the memory to the different queues and ports. * When DualNet is set to SK_TRUE all ports get the same amount of memory. - * Otherwise the first port gets most of the memory and all the + * Otherwise the first port gets most of the memory and all the * other ports just the required minimum. * This function can only be called when pAC->GIni.GIRamSize and * pAC->GIni.GIMacsFound have been initialized, usually this happens @@ -282,28 +404,38 @@ */ int SkGeInitAssignRamToQueues( -SK_AC *pAC, /* Adapter context */ +SK_AC *pAC, /* Adapter Context */ int ActivePort, /* Active Port in RLMT mode */ -SK_BOOL DualNet) /* adapter context */ +SK_BOOL DualNet) /* Dual Net active */ { int i; int UsedKilobytes; /* memory already assigned */ int ActivePortKilobytes; /* memory available for active port */ + int MinQueueSize; /* min. memory for queues */ SK_GEPORT *pGePort; UsedKilobytes = 0; if (ActivePort >= pAC->GIni.GIMacsFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n", ActivePort)); return(1); } - if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) + - ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) { + + MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE; + + if (MinQueueSize > pAC->GIni.GIRamSize) { + MinQueueSize = pAC->GIni.GIRamSize; + } + + if ((pAC->GIni.GIMacsFound * MinQueueSize + + RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > pAC->GIni.GIRamSize) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n", - pAC->GIni.GIRamSize)); + pAC->GIni.GIRamSize)); return(2); } @@ -313,13 +445,13 @@ for (i = 0; i < pAC->GIni.GIMacsFound; i++) { pGePort = &pAC->GIni.GP[i]; - + /* take away the minimum memory for active queues */ - ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + ActivePortKilobytes -= MinQueueSize; /* receive queue gets the minimum + 80% of the rest */ - pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB(( - ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100)) + pGePort->PRxQSize = SkGeRoundQueueSize(pAC, + (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE; ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); @@ -328,11 +460,11 @@ pGePort->PXSQSize = 0; /* asynchronous transmit queue */ - pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes + - SK_MIN_TXQ_SIZE); + pGePort->PXAQSize = SkGeRoundQueueSize(pAC, + ActivePortKilobytes + SK_MIN_TXQ_SIZE); } } - else { + else { /* Rlmt Mode or single link adapter */ /* Set standby queue size defaults for all standby ports */ @@ -354,30 +486,28 @@ /* assign it to the active port */ /* first take away the minimum memory */ - ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + ActivePortKilobytes -= MinQueueSize; pGePort = &pAC->GIni.GP[ActivePort]; /* receive queue get's the minimum + 80% of the rest */ - pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes * - (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE; + pGePort->PRxQSize = SkGeRoundQueueSize(pAC, + (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100) + + MinQueueSize/2; - ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + ActivePortKilobytes -= (pGePort->PRxQSize - MinQueueSize/2); /* synchronous transmit queue */ pGePort->PXSQSize = 0; /* asynchronous transmit queue */ - pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) + - SK_MIN_TXQ_SIZE; + pGePort->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) + + MinQueueSize/2; } -#ifdef VCPU - VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n", - pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize); -#endif /* VCPU */ return(0); } /* SkGeInitAssignRamToQueues */ + /****************************************************************************** * * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration @@ -388,12 +518,12 @@ * used ports. * This requirements must be fullfilled to have a valid configuration: * - The size of all queues must not exceed GIRamSize. - * - The queue sizes must be specified in units of 8 kB. + * - The queue sizes must be specified in units of 8 kB (Genesis & Yukon). * - The size of Rx queues of available ports must not be - * smaller than 16 kB. + * smaller than 16 kB (Genesis & Yukon) resp. 10 kB (Yukon-2). * - The size of at least one Tx queue (synch. or asynch.) - * of available ports must not be smaller than 16 kB - * when Jumbo Frames are used. + * of available ports must not be smaller than 16 kB (Genesis & Yukon), + * resp. 10 kB (Yukon-2) when Jumbo Frames are used. * - The RAM start and end addresses must not be changed * for ports which are already initialized. * Furthermore SkGeCheckQSize() defines the Start and End Addresses @@ -404,7 +534,7 @@ * 1: Queue Size Configuration invalid */ static int SkGeCheckQSize( -SK_AC *pAC, /* adapter context */ +SK_AC *pAC, /* Adapter Context */ int Port) /* port index */ { SK_GEPORT *pPrt; @@ -414,44 +544,51 @@ SK_U32 StartAddr; #ifndef SK_SLIM int UsedMem; /* total memory used (max. found ports) */ -#endif +#endif Rtv = 0; - + #ifndef SK_SLIM UsedMem = 0; + Rtv = 0; for (i = 0; i < pAC->GIni.GIMacsFound; i++) { pPrt = &pAC->GIni.GP[i]; - if ((pPrt->PRxQSize & QZ_UNITS) != 0 || - (pPrt->PXSQSize & QZ_UNITS) != 0 || - (pPrt->PXAQSize & QZ_UNITS) != 0) { + if (CHIP_ID_YUKON_2(pAC)) { + UsedMem = 0; + } + else if (((pPrt->PRxQSize & QZ_UNITS) != 0 || + (pPrt->PXSQSize & QZ_UNITS) != 0 || + (pPrt->PXAQSize & QZ_UNITS) != 0)) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); return(1); } - if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { +#ifndef SK_DIAG + if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE && + pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG); return(1); } - + /* * the size of at least one Tx queue (synch. or asynch.) has to be > 0. * if Jumbo Frames are used, this size has to be >= 16 kB. */ if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) || (pAC->GIni.GIPortUsage == SK_JUMBO_LINK && - ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || + ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG); return(1); } - +#endif /* !SK_DIAG */ + UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize; } - + if (UsedMem > pAC->GIni.GIRamSize) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); return(1); @@ -463,6 +600,14 @@ for (i = 0; i < pAC->GIni.GIMacsFound; i++) { pPrt = &pAC->GIni.GP[i]; + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n", + i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize)); + + if (CHIP_ID_YUKON_2(pAC)) { + StartAddr = 0; + } + /* Calculate/Check values for the receive queue */ Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr, &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd); @@ -502,8 +647,8 @@ * nothing */ static void SkGeInitMacArb( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { /* release local reset */ SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR); @@ -542,8 +687,8 @@ * nothing */ static void SkGeInitPktArb( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { /* release local reset */ SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR); @@ -582,14 +727,11 @@ * nothing */ static void SkGeInitMacFifo( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_U16 Word; -#ifdef VCPU - SK_U32 DWord; -#endif /* VCPU */ /* * For each FIFO: * - release local reset @@ -597,31 +739,29 @@ * - setup defaults for the control register * - enable the FIFO */ - + #ifdef GENESIS if (pAC->GIni.GIGenesis) { /* Configure Rx MAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF); SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD); - + /* Configure Tx MAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD); - + /* Enable frame flushing if jumbo frames used */ if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH); } } #endif /* GENESIS */ - + #ifdef YUKON if (pAC->GIni.GIYukon) { - /* set Rx GMAC FIFO Flush Mask */ - SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK); - + Word = (SK_U16)GMF_RX_CTRL_DEF; /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ @@ -629,23 +769,27 @@ Word &= ~GMF_RX_F_FL_ON; } - - /* Configure Rx MAC FIFO */ + + /* Configure Rx GMAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word); - - /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */ - SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); - - /* Configure Tx MAC FIFO */ + + /* set Rx GMAC FIFO Flush Mask (after clearing reset) */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK); + + Word = (SK_U16)RX_GMF_FL_THR_DEF; /* default: 0x0a -> 56 bytes) */ + + if (pAC->GIni.GIAsfEnabled) { + Word -= 2; /* for ASF: 0x08 -> 40 bytes) */ + } + + /* set Rx GMAC FIFO Flush Threshold (after clearing reset) */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word); + + /* Configure Tx GMAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF); - -#ifdef VCPU - SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord); - SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord); -#endif /* VCPU */ - + /* set Tx GMAC FIFO Almost Empty Threshold */ /* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */ } @@ -653,7 +797,7 @@ } /* SkGeInitMacFifo */ -#ifdef SK_LNK_SYNC_CNT +#ifdef SK_LNK_SYNC_CNT /****************************************************************************** * * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting @@ -674,8 +818,8 @@ * nothing */ void SkGeLoadLnkSyncCnt( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_U32 CntVal) /* Counter value */ { @@ -685,7 +829,7 @@ SK_BOOL IrqPend; /* stop counter */ - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP); + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_STOP); /* * ASIC problem: @@ -698,6 +842,7 @@ IrqPend = SK_FALSE; SK_IN32(IoC, B0_ISRC, &ISrc); SK_IN32(IoC, B0_IMSK, &OrgIMsk); + if (Port == MAC_1) { NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1; if ((ISrc & IS_LNK_SYNC_M1) != 0) { @@ -710,6 +855,7 @@ IrqPend = SK_TRUE; } } + if (!IrqPend) { SK_OUT32(IoC, B0_IMSK, NewIMsk); } @@ -718,15 +864,17 @@ SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal); /* start counter */ - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START); + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_START); if (!IrqPend) { - /* clear the unexpected IRQ, and restore the interrupt mask */ - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ); + /* clear the unexpected IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_CLR_IRQ); + + /* restore the interrupt mask */ SK_OUT32(IoC, B0_IMSK, OrgIMsk); } } /* SkGeLoadLnkSyncCnt*/ -#endif /* SK_LNK_SYNC_CNT */ +#endif /* SK_LNK_SYNC_CNT */ #if defined(SK_DIAG) || defined(SK_CFG_SYNC) /****************************************************************************** @@ -758,8 +906,8 @@ * synchronous queue is configured */ int SkGeCfgSync( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_U32 IntTime, /* Interval Timer Value in units of 8ns */ SK_U32 LimCount, /* Number of bytes to transfer during IntTime */ @@ -777,16 +925,16 @@ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); return(1); } - + if (pAC->GIni.GP[Port].PXSQSize == 0) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG); return(2); } - + /* calculate register values */ IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100; LimCount = LimCount / 8; - + if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); return(1); @@ -804,13 +952,13 @@ */ SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); - + SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime); SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount); - + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC))); - + if (IntTime != 0 || LimCount != 0) { SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC); } @@ -831,10 +979,10 @@ * Returns: * nothing */ -static void DoInitRamQueue( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -int QuIoOffs, /* Queue IO Address Offset */ +void DoInitRamQueue( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int QuIoOffs, /* Queue I/O Address Offset */ SK_U32 QuStartAddr, /* Queue Start Address */ SK_U32 QuEndAddr, /* Queue End Address */ int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ @@ -867,8 +1015,7 @@ /* continue with SK_RX_BRAM_Q */ case SK_RX_BRAM_Q: - /* write threshold for Rx Queue */ - + /* write threshold for Rx Queue (Pause packets) */ SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal); SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal); @@ -911,8 +1058,8 @@ * nothing */ static void SkGeInitRamBufs( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; @@ -920,7 +1067,7 @@ pPrt = &pAC->GIni.GP[Port]; - if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { + if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) { RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ } else { @@ -929,10 +1076,10 @@ DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart, pPrt->PRxQRamEnd, RxQType); - + DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart, pPrt->PXsQRamEnd, SK_TX_RAM_Q); - + DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart, pPrt->PXaQRamEnd, SK_TX_RAM_Q); @@ -953,26 +1100,37 @@ * nothing */ void SkGeInitRamIface( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { - /* release local reset */ - SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR); + int i; + int RamBuffers; - /* configure timeout values */ - SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53); + if (CHIP_ID_YUKON_2(pAC)) { + RamBuffers = pAC->GIni.GIMacsFound; + } + else { + RamBuffers = 1; + } + + for (i = 0; i < RamBuffers; i++) { + /* release local reset */ + SK_OUT16(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); + /* configure timeout values */ + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); + } } /* SkGeInitRamIface */ @@ -987,8 +1145,8 @@ * nothing */ static void SkGeInitBmu( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; @@ -999,29 +1157,63 @@ RxWm = SK_BMU_RX_WM; TxWm = SK_BMU_TX_WM; - - if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { - /* for better performance */ - RxWm /= 2; - TxWm /= 2; - } - /* Rx Queue: Release all local resets and set the watermark */ - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); + if (CHIP_ID_YUKON_2(pAC)) { - /* - * Tx Queue: Release all local resets if the queue is used ! - * set watermark - */ - if (pPrt->PXSQSize != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); + if (pAC->GIni.GIPciBus == SK_PEX_BUS) { + /* for better performance set it to 128 */ + RxWm = SK_BMU_RX_WM_PEX; + } + + /* Rx Queue: Release all local resets and set the watermark */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm); + + /* + * Tx Queue: Release all local resets if the queue is used ! + * set watermark + */ + if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) { + /* Yukon-EC doesn't have a synchronous Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm); + } + + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm); + } } - - if (pPrt->PXAQSize != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); + else { + if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { + /* for better performance */ + RxWm /= 2; + TxWm /= 2; + } + + /* Rx Queue: Release all local resets and set the watermark */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); + + /* + * Tx Queue: Release all local resets if the queue is used ! + * set watermark + */ + if (pPrt->PXSQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); + } + + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); + } } /* * Do NOT enable the descriptor poll timers here, because @@ -1045,20 +1237,29 @@ */ static SK_U32 TestStopBit( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int QuIoOffs) /* Queue IO Address Offset */ +SK_IOC IoC, /* I/O Context */ +int QuIoOffs) /* Queue I/O Address Offset */ { SK_U32 QuCsr; /* CSR contents */ SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); - if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { - /* Stop Descriptor overridden by start command */ - SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); + if (CHIP_ID_YUKON_2(pAC)) { + if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) { + /* Stop Descriptor overridden by start command */ + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP); - SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + } + } + else { + if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { + /* Stop Descriptor overridden by start command */ + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); + + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + } } - return(QuCsr); } /* TestStopBit */ @@ -1142,56 +1343,83 @@ * SWITCH_PORT. */ void SkGeStopPort( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* I/O context */ -int Port, /* port to stop (MAC_1 + n) */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port to stop (MAC_1 + n) */ int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ { -#ifndef SK_DIAG - SK_EVPARA Para; -#endif /* !SK_DIAG */ SK_GEPORT *pPrt; - SK_U32 DWord; + SK_U32 RxCsr; SK_U32 XsCsr; SK_U32 XaCsr; SK_U64 ToutStart; + SK_U32 CsrStart; + SK_U32 CsrStop; + SK_U32 CsrIdle; + SK_U32 CsrTest; + SK_U8 rsl; /* FIFO read shadow level */ + SK_U8 rl; /* FIFO read level */ int i; int ToutCnt; pPrt = &pAC->GIni.GP[Port]; + /* set the proper values of Q_CSR register layout depending on the chip id */ + if (CHIP_ID_YUKON_2(pAC)) { + CsrStart = BMU_START; + CsrStop = BMU_STOP; + CsrIdle = BMU_IDLE; + CsrTest = BMU_IDLE; + } + else { + CsrStart = CSR_START; + CsrStop = CSR_STOP; + CsrIdle = CSR_SV_IDLE; + CsrTest = CSR_SV_IDLE | CSR_STOP; + } + if ((Dir & SK_STOP_TX) != 0) { - /* disable receiver and transmitter */ - SkMacRxTxDisable(pAC, IoC, Port); - + + if (!pAC->GIni.GIAsfEnabled) { + /* disable receiver and transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + } + /* stop both transmit queues */ /* * If the BMU is in the reset state CSR_STOP will terminate * immediately. */ - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP); - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop); ToutStart = SkOsGetTime(pAC); ToutCnt = 0; do { - /* - * Clear packet arbiter timeout to make sure - * this loop will terminate. - */ - SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? - PA_CLR_TO_TX1 : PA_CLR_TO_TX2)); - - /* - * If the transfer stucks at the MAC the STOP command will not - * terminate if we don't flush the XMAC's transmit FIFO ! - */ - SkMacFlushTxFifo(pAC, IoC, Port); +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + /* Clear Tx packet arbiter timeout IRQ */ + SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? + PA_CLR_TO_TX1 : PA_CLR_TO_TX2)); - XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); + /* + * If the transfer stucks at the MAC the STOP command will not + * terminate if we don't flush the XMAC's transmit FIFO ! + */ + SkMacFlushTxFifo(pAC, IoC, Port); + } +#endif /* GENESIS */ + XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); + if (HW_SYNC_TX_SUPPORTED(pAC)) { + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); + } + else { + XsCsr = XaCsr; + } + if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) { /* * Timeout of 1/18 second reached. @@ -1199,18 +1427,12 @@ */ ToutCnt++; if (ToutCnt > 1) { - /* Might be a problem when the driver event handler - * calls StopPort again. XXX. + /* + * If BMU stop doesn't terminate, we assume + * we have a stable state and can reset the + * BMU, Pref Unit, and RAM buffer now. */ - - /* Fatal Error, Loop aborted */ - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018, - SKERR_HWI_E018MSG); -#ifndef SK_DIAG - Para.Para64 = Port; - SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); -#endif /* !SK_DIAG */ - return; + break; /* ====> leave do/while loop here */ } /* * Cache incoherency workaround: Assume a start command @@ -1218,48 +1440,84 @@ */ ToutStart = SkOsGetTime(pAC); - if ((XsCsr & CSR_STOP) != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START); + if ((XsCsr & CsrStop) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart); + } + if ((XaCsr & CsrStop) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart); + } + + /* + * After the previous operations the X(s|a)Csr does no + * longer contain the proper values + */ + XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); + + if (HW_SYNC_TX_SUPPORTED(pAC)) { + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); } - if ((XaCsr & CSR_STOP) != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START); + else { + XsCsr = XaCsr; } } /* * Because of the ASIC problem report entry from 21.08.1998 it is * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. + * (valid for GENESIS only) */ - } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE || - (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + } while (((XsCsr & CsrTest) != CsrIdle || + (XaCsr & CsrTest) != CsrIdle)); + + if (pAC->GIni.GIAsfEnabled) { - /* Reset the MAC depending on the RstMode */ - if (RstMode == SK_SOFT_RST) { - SkMacSoftRst(pAC, IoC, Port); + pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP : + SK_PRT_RESET; } else { - SkMacHardRst(pAC, IoC, Port); + /* Reset the MAC depending on the RstMode */ + if (RstMode == SK_SOFT_RST) { + SkMacSoftRst(pAC, IoC, Port); + } + else { + SkMacHardRst(pAC, IoC, Port); + } } - + /* Disable Force Sync bit and Enable Alloc bit */ SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); - + /* Stop Interval Timer and Limit Counter of Tx Arbiter */ SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L); SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L); /* Perform a local reset of the port's Tx path */ + if (CHIP_ID_YUKON_2(pAC)) { + /* Reset the PCI FIFO of the async Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), + BMU_RST_SET | BMU_FIFO_RST); + /* Reset the PCI FIFO of the sync Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), + BMU_RST_SET | BMU_FIFO_RST); + /* Reset the Tx prefetch units */ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG), + PREF_UNIT_RST_SET); + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG), + PREF_UNIT_RST_SET); + } + else { + /* Reset the PCI FIFO of the async Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); + /* Reset the PCI FIFO of the sync Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); + } - /* Reset the PCI FIFO of the async Tx queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); - /* Reset the PCI FIFO of the sync Tx queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); /* Reset the RAM Buffer async Tx queue */ SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET); /* Reset the RAM Buffer sync Tx queue */ SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET); - + /* Reset Tx MAC FIFO */ #ifdef GENESIS if (pAC->GIni.GIGenesis) { @@ -1271,71 +1529,114 @@ SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS); } #endif /* GENESIS */ - + #ifdef YUKON - if (pAC->GIni.GIYukon) { - /* Reset TX MAC FIFO */ + if (pAC->GIni.GIYukon && !pAC->GIni.GIAsfEnabled) { + /* Reset Tx MAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); } + + /* set Pause Off */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF); #endif /* YUKON */ } if ((Dir & SK_STOP_RX) != 0) { - /* - * The RX Stop Command will not terminate if no buffers - * are queued in the RxD ring. But it will always reach - * the Idle state. Therefore we can use this feature to - * stop the transfer of received packets. - */ - /* stop the port's receive queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP); - i = 100; - do { + if (CHIP_ID_YUKON_2(pAC)) { /* - * Clear packet arbiter timeout to make sure - * this loop will terminate + * The RX Stop command will not work for Yukon-2 if the BMU does not + * reach the end of packet and since we can't make sure that we have + * incoming data, we must reset the BMU while it is not during a DMA + * transfer. Since it is possible that the RX path is still active, + * the RX RAM buffer will be stopped first, so any possible incoming + * data will not trigger a DMA. After the RAM buffer is stopped, the + * BMU is polled until any DMA in progress is ended and only then it + * will be reset. */ - SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? - PA_CLR_TO_RX1 : PA_CLR_TO_RX2)); - DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff); + /* Disable the RAM Buffer receive queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD); - /* timeout if i==0 (bug fix for #10748) */ - if (--i == 0) { - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024, - SKERR_HWI_E024MSG); - break; - } + i = 0xffff; + while (--i) { + SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RSL), &rsl); + SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RL), &rl); + + if (rsl == rl) { + break; + } + } + + /* + * If the rx side is blocked the above loop + * cannot terminate. But, if there was any traffic + * it should be terminated, now. However, stop the + * RX BMU and prefetch unit! + */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), + BMU_RST_SET |